intel/compiler: Allow ternary add to promote source to immediate

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11596>

diff --git a/src/intel/compiler/brw_fs_combine_constants.cpp b/src/intel/compiler/brw_fs_combine_constants.cpp
index ff5f1ec..43c01bc 100644 (file)
--- a/src/intel/compiler/brw_fs_combine_constants.cpp
+++ b/src/intel/compiler/brw_fs_combine_constants.cpp
@@ -79,6 +79,7 @@ must_promote_imm(const struct intel_device_info *devinfo, const fs_inst *inst)
    case SHADER_OPCODE_POW:
       return devinfo->ver < 8;
    case BRW_OPCODE_MAD:
+   case BRW_OPCODE_ADD3:
    case BRW_OPCODE_LRP:
       return true;
    default:
@@ -336,9 +337,34 @@ representable_as_hf(float f, uint16_t *hf)
 }
 
 static bool
+representable_as_w(int d, int16_t *w)
+{
+   int res = ((d & 0xffff8000) + 0x8000) & 0xffff7fff;
+   if (!res) {
+      *w = d;
+      return true;
+   }
+
+   return false;
+}
+
+static bool
+representable_as_uw(unsigned ud, uint16_t *uw)
+{
+   if (!(ud & 0xffff0000)) {
+      *uw = ud;
+      return true;
+   }
+
+   return false;
+}
+
+static bool
 supports_src_as_imm(const struct intel_device_info *devinfo, enum opcode op)
 {
    switch (op) {
+   case BRW_OPCODE_ADD3:
+      return devinfo->verx10 >= 125;
    case BRW_OPCODE_MAD:
       return devinfo->ver == 12 && devinfo->verx10 < 125;
    default:
@@ -368,6 +394,20 @@ can_promote_src_as_imm(const struct intel_device_info *devinfo, fs_inst *inst,
          return true;
       }
    }
+   case BRW_REGISTER_TYPE_W: {
+      int16_t w;
+      if (representable_as_w(inst->src[src_idx].d, &w)) {
+         inst->src[src_idx] = brw_imm_w(w);
+         return true;
+      }
+   }
+   case BRW_REGISTER_TYPE_UW: {
+      uint16_t uw;
+      if (representable_as_uw(inst->src[src_idx].ud, &uw)) {
+         inst->src[src_idx] = brw_imm_uw(uw);
+         return true;
+      }
+   }
    default:
       return false;
    }