gallium/radeon: drop support for LLVM 3.4

This allows using the new tex instrinsics unconditionally.

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>

diff --git a/configure.ac b/configure.ac
index 1db5b28..d8e5643 100644 (file)
--- a/configure.ac
+++ b/configure.ac
@@ -2073,7 +2073,7 @@ radeon_llvm_check() {
     if test "x$enable_gallium_llvm" != "xyes"; then
         AC_MSG_ERROR([--enable-gallium-llvm is required when building $1])
     fi
-    llvm_check_version_for "3" "4" "2" $1 
+    llvm_check_version_for "3" "5" "0" $1
     if test true && $LLVM_CONFIG --targets-built | grep -iqvw $amdgpu_llvm_target_name ; then
         AC_MSG_ERROR([LLVM $amdgpu_llvm_target_name not enabled in your LLVM build.])
     fi

diff --git a/src/gallium/drivers/radeon/r600_pipe_common.c b/src/gallium/drivers/radeon/r600_pipe_common.c
index ed5d1da..1302b5a 100644 (file)
--- a/src/gallium/drivers/radeon/r600_pipe_common.c
+++ b/src/gallium/drivers/radeon/r600_pipe_common.c
@@ -531,11 +531,7 @@ const char *r600_get_llvm_processor_name(enum radeon_family family)
        case CHIP_KAVERI: return "kaveri";
        case CHIP_HAWAII: return "hawaii";
        case CHIP_MULLINS:
-#if HAVE_LLVM >= 0x0305
                return "mullins";
-#else
-               return "kabini";
-#endif
        case CHIP_TONGA: return "tonga";
        case CHIP_ICELAND: return "iceland";
        case CHIP_CARRIZO: return "carrizo";

diff --git a/src/gallium/drivers/radeon/radeon_llvm_emit.c b/src/gallium/drivers/radeon/radeon_llvm_emit.c
index 0002559..3acbd02 100644 (file)
--- a/src/gallium/drivers/radeon/radeon_llvm_emit.c
+++ b/src/gallium/drivers/radeon/radeon_llvm_emit.c
@@ -122,8 +122,6 @@ LLVMTargetRef radeon_llvm_get_r600_target(const char *triple)
        return target;
 }
 
-#if HAVE_LLVM >= 0x0305
-
 static void radeonDiagnosticHandler(LLVMDiagnosticInfoRef di, void *context)
 {
        if (LLVMGetDiagInfoSeverity(di) == LLVMDSError) {
@@ -136,8 +134,6 @@ static void radeonDiagnosticHandler(LLVMDiagnosticInfoRef di, void *context)
        }
 }
 
-#endif
-
 /**
  * Compile an LLVM module to machine code.
  *
@@ -180,9 +176,7 @@ unsigned radeon_llvm_compile(LLVMModuleRef M, struct radeon_shader_binary *binar
        /* Setup Diagnostic Handler*/
        llvm_ctx = LLVMGetModuleContext(M);
 
-#if HAVE_LLVM >= 0x0305
        LLVMContextSetDiagnosticHandler(llvm_ctx, radeonDiagnosticHandler, &rval);
-#endif
        rval = 0;
 
        /* Compile IR*/

diff --git a/src/gallium/drivers/radeon/radeon_setup_tgsi_llvm.c b/src/gallium/drivers/radeon/radeon_setup_tgsi_llvm.c
index 5669470..2e9a013 100644 (file)
--- a/src/gallium/drivers/radeon/radeon_setup_tgsi_llvm.c
+++ b/src/gallium/drivers/radeon/radeon_setup_tgsi_llvm.c
@@ -1520,8 +1520,7 @@ void radeon_llvm_context_init(struct radeon_llvm_context * ctx)
        bld_base->op_actions[TGSI_OPCODE_POW].intr_name = "llvm.pow.f32";
        bld_base->op_actions[TGSI_OPCODE_ROUND].emit = build_tgsi_intrinsic_nomem;
        bld_base->op_actions[TGSI_OPCODE_ROUND].intr_name = "llvm.AMDIL.round.nearest.";
-       bld_base->op_actions[TGSI_OPCODE_RSQ].intr_name =
-               HAVE_LLVM >= 0x0305 ? "llvm.AMDGPU.rsq.clamped.f32" : "llvm.AMDGPU.rsq";
+       bld_base->op_actions[TGSI_OPCODE_RSQ].intr_name = "llvm.AMDGPU.rsq.clamped.f32";
        bld_base->op_actions[TGSI_OPCODE_RSQ].emit = build_tgsi_intrinsic_nomem;
        bld_base->op_actions[TGSI_OPCODE_SGE].emit = emit_cmp;
        bld_base->op_actions[TGSI_OPCODE_SEQ].emit = emit_cmp;

diff --git a/src/gallium/drivers/radeonsi/si_compute.c b/src/gallium/drivers/radeonsi/si_compute.c
index e3caf5e..ed9147c 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_compute.c
+++ b/src/gallium/drivers/radeonsi/si_compute.c
@@ -33,14 +33,11 @@
 #include "sid.h"
 
 #define MAX_GLOBAL_BUFFERS 20
-#if HAVE_LLVM < 0x0305
-#define NUM_USER_SGPRS 2
-#else
+
 /* XXX: Even though we don't pass the scratch buffer via user sgprs any more
  * LLVM still expects that we specify 4 USER_SGPRS so it can remain compatible
  * with older mesa. */
 #define NUM_USER_SGPRS 4
-#endif
 
 struct si_compute {
        struct si_context *ctx;

diff --git a/src/gallium/drivers/radeonsi/si_pipe.c b/src/gallium/drivers/radeonsi/si_pipe.c
index 85ade31..9094427 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_pipe.c
+++ b/src/gallium/drivers/radeonsi/si_pipe.c
@@ -282,6 +282,8 @@ static int si_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
        case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
        case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
        case PIPE_CAP_DEPTH_BOUNDS_TEST:
+       case PIPE_CAP_TEXTURE_QUERY_LOD:
+       case PIPE_CAP_TEXTURE_GATHER_SM5:
                return 1;
 
        case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
@@ -304,6 +306,7 @@ static int si_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
 
        case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
        case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
+       case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
                return 4;
 
        case PIPE_CAP_GLSL_FEATURE_LEVEL:
@@ -312,12 +315,6 @@ static int si_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
        case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
                return MIN2(sscreen->b.info.vram_size, 0xFFFFFFFF);
 
-       case PIPE_CAP_TEXTURE_QUERY_LOD:
-       case PIPE_CAP_TEXTURE_GATHER_SM5:
-               return HAVE_LLVM >= 0x0305;
-       case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
-               return HAVE_LLVM >= 0x0305 ? 4 : 0;
-
        /* Unsupported features. */
        case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
        case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:

diff --git a/src/gallium/drivers/radeonsi/si_shader.c b/src/gallium/drivers/radeonsi/si_shader.c
index ab5b3ee..9a216c7 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_shader.c
+++ b/src/gallium/drivers/radeonsi/si_shader.c
@@ -2276,7 +2276,7 @@ static void tex_fetch_args(
        unsigned sampler_src;
        unsigned sampler_index;
        unsigned num_deriv_channels = 0;
-       bool has_offset = HAVE_LLVM >= 0x0305 ? inst->Texture.NumOffsets > 0 : false;
+       bool has_offset = inst->Texture.NumOffsets > 0;
        LLVMValueRef res_ptr, samp_ptr, fmask_ptr = NULL;
 
        sampler_src = emit_data->inst->Instruction.NumSrcRegs - 1;
@@ -2682,8 +2682,7 @@ static void build_tex_intrinsic(const struct lp_build_tgsi_action * action,
        unsigned opcode = emit_data->inst->Instruction.Opcode;
        unsigned target = emit_data->inst->Texture.Texture;
        char intr_name[127];
-       bool has_offset = HAVE_LLVM >= 0x0305 ?
-                               emit_data->inst->Texture.NumOffsets > 0 : false;
+       bool has_offset = emit_data->inst->Texture.NumOffsets > 0;
 
        if (target == TGSI_TEXTURE_BUFFER) {
                emit_data->output[emit_data->chan] = lp_build_intrinsic(