drm/i915: Parametrize MOCS registers

v2: Use for_each_ring() (Chris)

Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Francisco Jerez <currojerez@riseup.net>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1446725633-6419-1-git-send-email-ville.syrjala@linux.intel.com
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 47fdc94..fc586fb 100644 (file)
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8165,12 +8165,12 @@ enum skl_disp_power_wells {
 #define _PALETTE_B (dev_priv->info.display_mmio_offset + 0xa800)
 
 /* MOCS (Memory Object Control State) registers */
-#define GEN9_LNCFCMOCS0                0xb020  /* L3 Cache Control base */
+#define GEN9_LNCFCMOCS(i)      (0xb020 + (i) * 4)      /* L3 Cache Control */
 
-#define GEN9_GFX_MOCS_0                0xc800  /* Graphics MOCS base register*/
-#define GEN9_MFX0_MOCS_0       0xc900  /* Media 0 MOCS base register*/
-#define GEN9_MFX1_MOCS_0       0xca00  /* Media 1 MOCS base register*/
-#define GEN9_VEBOX_MOCS_0      0xcb00  /* Video MOCS base register*/
-#define GEN9_BLT_MOCS_0                0xcc00  /* Blitter MOCS base register*/
+#define GEN9_GFX_MOCS(i)       (0xc800 + (i) * 4)      /* Graphics MOCS registers */
+#define GEN9_MFX0_MOCS(i)      (0xc900 + (i) * 4)      /* Media 0 MOCS registers */
+#define GEN9_MFX1_MOCS(i)      (0xca00 + (i) * 4)      /* Media 1 MOCS registers */
+#define GEN9_VEBOX_MOCS(i)     (0xcb00 + (i) * 4)      /* Video MOCS registers */
+#define GEN9_BLT_MOCS(i)       (0xcc00 + (i) * 4)      /* Blitter MOCS registers */
 
 #endif /* _I915_REG_H_ */

diff --git a/drivers/gpu/drm/i915/intel_mocs.c b/drivers/gpu/drm/i915/intel_mocs.c
index b258a2a..d546319 100644 (file)
--- a/drivers/gpu/drm/i915/intel_mocs.c
+++ b/drivers/gpu/drm/i915/intel_mocs.c
@@ -159,11 +159,30 @@ static bool get_mocs_settings(struct drm_device *dev,
        return result;
 }
 
+static uint32_t mocs_register(enum intel_ring_id ring, int index)
+{
+       switch (ring) {
+       case RCS:
+               return GEN9_GFX_MOCS(index);
+       case VCS:
+               return GEN9_MFX0_MOCS(index);
+       case BCS:
+               return GEN9_BLT_MOCS(index);
+       case VECS:
+               return GEN9_VEBOX_MOCS(index);
+       case VCS2:
+               return GEN9_MFX1_MOCS(index);
+       default:
+               MISSING_CASE(ring);
+               return 0;
+       }
+}
+
 /**
  * emit_mocs_control_table() - emit the mocs control table
  * @req:       Request to set up the MOCS table for.
  * @table:     The values to program into the control regs.
- * @reg_base:  The base for the engine that needs to be programmed.
+ * @ring:      The engine for whom to emit the registers.
  *
  * This function simply emits a MI_LOAD_REGISTER_IMM command for the
  * given table starting at the given address.
@@ -172,7 +191,7 @@ static bool get_mocs_settings(struct drm_device *dev,
  */
 static int emit_mocs_control_table(struct drm_i915_gem_request *req,
                                   const struct drm_i915_mocs_table *table,
-                                  u32 reg_base)
+                                  enum intel_ring_id ring)
 {
        struct intel_ringbuffer *ringbuf = req->ringbuf;
        unsigned int index;
@@ -191,7 +210,7 @@ static int emit_mocs_control_table(struct drm_i915_gem_request *req,
                                MI_LOAD_REGISTER_IMM(GEN9_NUM_MOCS_ENTRIES));
 
        for (index = 0; index < table->size; index++) {
-               intel_logical_ring_emit(ringbuf, reg_base + index * 4);
+               intel_logical_ring_emit(ringbuf, mocs_register(ring, index));
                intel_logical_ring_emit(ringbuf,
                                        table->table[index].control_value);
        }
@@ -205,7 +224,7 @@ static int emit_mocs_control_table(struct drm_i915_gem_request *req,
         * that value to all the used entries.
         */
        for (; index < GEN9_NUM_MOCS_ENTRIES; index++) {
-               intel_logical_ring_emit(ringbuf, reg_base + index * 4);
+               intel_logical_ring_emit(ringbuf, mocs_register(ring, index));
                intel_logical_ring_emit(ringbuf, table->table[0].control_value);
        }
 
@@ -253,7 +272,7 @@ static int emit_mocs_l3cc_table(struct drm_i915_gem_request *req,
                value = (table->table[count].l3cc_value & 0xffff) |
                        ((table->table[count + 1].l3cc_value & 0xffff) << 16);
 
-               intel_logical_ring_emit(ringbuf, GEN9_LNCFCMOCS0 + i * 4);
+               intel_logical_ring_emit(ringbuf, GEN9_LNCFCMOCS(i));
                intel_logical_ring_emit(ringbuf, value);
        }
 
@@ -270,7 +289,7 @@ static int emit_mocs_l3cc_table(struct drm_i915_gem_request *req,
         * they are reserved by the hardware.
         */
        for (; i < GEN9_NUM_MOCS_ENTRIES / 2; i++) {
-               intel_logical_ring_emit(ringbuf, GEN9_LNCFCMOCS0 + i * 4);
+               intel_logical_ring_emit(ringbuf, GEN9_LNCFCMOCS(i));
                intel_logical_ring_emit(ringbuf, value);
 
                value = filler;
@@ -304,26 +323,16 @@ int intel_rcs_context_init_mocs(struct drm_i915_gem_request *req)
        int ret;
 
        if (get_mocs_settings(req->ring->dev, &t)) {
-               /* Program the control registers */
-               ret = emit_mocs_control_table(req, &t, GEN9_GFX_MOCS_0);
-               if (ret)
-                       return ret;
-
-               ret = emit_mocs_control_table(req, &t, GEN9_MFX0_MOCS_0);
-               if (ret)
-                       return ret;
+               struct drm_i915_private *dev_priv = req->i915;
+               struct intel_engine_cs *ring;
+               enum intel_ring_id ring_id;
 
-               ret = emit_mocs_control_table(req, &t, GEN9_MFX1_MOCS_0);
-               if (ret)
-                       return ret;
-
-               ret = emit_mocs_control_table(req, &t, GEN9_VEBOX_MOCS_0);
-               if (ret)
-                       return ret;
-
-               ret = emit_mocs_control_table(req, &t, GEN9_BLT_MOCS_0);
-               if (ret)
-                       return ret;
+               /* Program the control registers */
+               for_each_ring(ring, dev_priv, ring_id) {
+                       ret = emit_mocs_control_table(req, &t, ring_id);
+                       if (ret)
+                               return ret;
+               }
 
                /* Now program the l3cc registers */
                ret = emit_mocs_l3cc_table(req, &t);