riscv: fix riscv64 unrecognized opcode build error

Considering older gcc version, "imafd" has to be changed
to "g", in order for asm to handle "zicsr" and "zifencei"
extensions.

Support for the mentioned extensions has been added
in GCC 11.1, hence this commit may be removed
after GCC update.

The lack of this causes following errors:
Error: unrecognized opcode `csrr a5,0xc01'
Error: unrecognized opcode `csrr a2,0xc01'

Change-Id: I0768a7b1255c828c4fc319f74f2783bc7e1581bf
Signed-off-by: Marek Szulc <m.szulc3@samsung.com>
Signed-off-by: Łukasz Stelmach <l.stelmach@samsung.com>

diff --git a/arch/riscv/Makefile b/arch/riscv/Makefile
index 3cb876f..4114bda 100644 (file)
--- a/arch/riscv/Makefile
+++ b/arch/riscv/Makefile
@@ -55,6 +55,7 @@ endif
 riscv-march-$(CONFIG_ARCH_RV32I)       := rv32ima
 riscv-march-$(CONFIG_ARCH_RV64I)       := rv64ima
 riscv-march-$(CONFIG_FPU)              := $(riscv-march-y)fd
+riscv-march-y                          := $(subst imafd,g,$(riscv-march-y))
 riscv-march-$(CONFIG_RISCV_ISA_C)      := $(riscv-march-y)c
 
 ifdef CONFIG_TOOLCHAIN_NEEDS_OLD_ISA_SPEC