intel/genxml: correct bit fields in CACHE_MODE_0 reg for gen11

correct bit fields information of CACHE_MODE_0 reg in current gen11.xml

Signed-off-by: Dongwon Kim <dongwon.kim@intel.com>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>

diff --git a/src/intel/genxml/gen11.xml b/src/intel/genxml/gen11.xml
index 1579345..c177450 100644 (file)
--- a/src/intel/genxml/gen11.xml
+++ b/src/intel/genxml/gen11.xml
@@ -6818,30 +6818,28 @@
   </register>
 
   <register name="CACHE_MODE_0" length="1" num="0x7000">
-    <field name="Null tile fix disable" start="0" end="0" type="bool"/>
+    <field name="Disable Byte sharing for 3D TYF LOD1 surfaces for 32/64/128 bpp" start="0" end="0" type="bool"/>
     <field name="Disable clock gating in the pixel backend" start="1" end="1" type="bool"/>
-    <field name="Hierarchical Z RAW Stall Optimization Disable" start="2" end="2" type="bool"/>
+    <field name="Hierarchical Z Disable" start="3" end="3" type="bool"/>
     <field name="RCC Eviction Policy" start="4" end="4" type="bool"/>
-    <field name="STC PMA Optimization Enable" start="5" end="5" type="bool"/>
-    <field name="Sampler L2 Request Arbitration" start="6" end="7" type="uint">
-      <value name="Round Robin" value="0"/>
-      <value name="Fetch are Highest Priority" value="1"/>
-      <value name="Constants are Highest Priority" value="2"/>
-    </field>
+    <field name="STC PMA Optimization Disable" start="5" end="5" type="bool"/>
+    <field name="STC Read-Hit Wonly Optimization Disable" start="6" end="6" type="bool"/>
+    <field name="Depth Related Cache Pipelined Flush Disable" start="8" end="8" type="bool"/>
     <field name="Sampler L2 TLB Prefetch Enable" start="9" end="9" type="bool"/>
-    <field name="Sampler Set Remapping for 3D Disable" start="11" end="11" type="bool"/>
+    <field name="RCZ PMA Not-Promoted Allocation stall optimization Disable due to change in depth parameters" start="10" end="10" type="bool"/>
     <field name="MSAA Compression Plane Number Threshold for eLLC" start="12" end="14" type="uint"/>
-    <field name="Sampler L2 Disable" start="15" end="15" type="bool"/>
-    <field name="Null tile fix disable Mask" start="16" end="16" type="bool"/>
+    <field name="Disable Repacking for Compression" start="15" end="15" type="bool"/>
+    <field name="Disable Byte sharing for 3D TYF LOD1 surfaces for 32/64/128 bpp Mask" start="16" end="16" type="bool"/>
     <field name="Disable clock gating in the pixel backend Mask" start="17" end="17" type="bool"/>
-    <field name="Hierarchical Z RAW Stall Optimization Disable Mask" start="18" end="18" type="bool"/>
+    <field name="Hierarchical Z Disable Mask" start="19" end="19" type="bool"/>
     <field name="RCC Eviction Policy Mask" start="20" end="20" type="bool"/>
-    <field name="STC PMA Optimization Enable Mask" start="21" end="21" type="bool"/>
-    <field name="Sampler L2 Request Arbitration Mask" start="22" end="23" type="uint"/>
+    <field name="STC PMA Optimization Disable Mask" start="21" end="21" type="bool"/>
+    <field name="STC Read-Hit Wonly Optimization Disable Mask" start="22" end="22" type="bool"/>
+    <field name="Depth Related Cache Pipelined Flush Disable Mask" start="24" end="24" type="bool"/>
     <field name="Sampler L2 TLB Prefetch Enable Mask" start="25" end="25" type="bool"/>
-    <field name="Sampler Set Remapping for 3D Disable Mask" start="27" end="27" type="bool"/>
+    <field name="RCZ PMA Not-Promoted Allocation stall optimization Disable due to change in depth parameters Mask" start="26" end="26" type="bool"/>
     <field name="MSAA Compression Plane Number Threshold for eLLC Mask" start="28" end="30" type="uint"/>
-    <field name="Sampler L2 Disable Mask" start="31" end="31" type="bool"/>
+    <field name="Disable Repacking for Compression Mask" start="31" end="31" type="bool"/>
   </register>
 
   <register name="CACHE_MODE_1" length="1" num="0x7004">