Reviewers: efriedma, sdesmalen, kparzysz
Reviewed By: kparzysz
Subscribers: tschuett, hiraditya, rkruppe, psnobl, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D77899
if (Src->isVectorTy()) {
VectorType *VecTy = cast<VectorType>(Src);
- unsigned VecWidth = VecTy->getBitWidth();
+ unsigned VecWidth = VecTy->getPrimitiveSizeInBits().getFixedSize();
if (useHVX() && isTypeForHVX(VecTy)) {
unsigned RegWidth = getRegisterBitWidth(true);
assert(RegWidth && "Non-zero vector register width expected");