drm/i915/xelp: Implement Wa_1606376872

Wa_1606376872 applies to all Xe_LP IPs except DG1.

Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20230307032238.300674-1-gustavo.sousa@intel.com

diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
index 423e3e9..97a6094 100644 (file)
--- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
@@ -480,6 +480,9 @@
 #define   HDC_FORCE_NON_COHERENT               (1 << 4)
 #define   HDC_BARRIER_PERFORMANCE_DISABLE      (1 << 10)
 
+#define COMMON_SLICE_CHICKEN4                  _MMIO(0x7300)
+#define   DISABLE_TDC_LOAD_BALANCING_CALC      REG_BIT(6)
+
 #define GEN8_HDC_CHICKEN1                      _MMIO(0x7304)
 
 #define GEN11_COMMON_SLICE_CHICKEN3            _MMIO(0x7304)

diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 5a1c56c..cf05eec 100644 (file)
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -743,9 +743,13 @@ static void gen12_ctx_workarounds_init(struct intel_engine_cs *engine,
               FF_MODE2_GS_TIMER_224,
               0, false);
 
-       if (!IS_DG1(i915))
+       if (!IS_DG1(i915)) {
                /* Wa_1806527549 */
                wa_masked_en(wal, HIZ_CHICKEN, HZ_DEPTH_TEST_LE_GE_OPT_DISABLE);
+
+               /* Wa_1606376872 */
+               wa_masked_en(wal, COMMON_SLICE_CHICKEN4, DISABLE_TDC_LOAD_BALANCING_CALC);
+       }
 }
 
 static void dg1_ctx_workarounds_init(struct intel_engine_cs *engine,