ARM: dts: ixp4xx: Add device trees for Coyote and IXDPG425

This adds device trees for the ADI Engineering Coyote and the
Intel IXDPG425 reference design. The ethernet set-up on the
IXDPG425 is a bit dubious because I think it uses a DSA
switch chip, but this is a good as it gets right now.

The Coyote boardfile claims an IDE port exist at 0xFFFE1000
but the implementation does not use this. If you have the
board and can/want to test, please contact me.

Cc: Deepak Saxena <dsaxena@plexity.net>
Cc: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
Cc: Zoltan HERPAI <wigyori@uid0.hu>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>

diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index f1f189e3a9386a5cafd09ba43112deb3e982df5f..ac8a4a77584d3eb773f9aebcb13de235300f8ad9 100644 (file)
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -245,6 +245,8 @@ dtb-$(CONFIG_ARCH_IXP4XX) += \
        intel-ixp42x-ixdp425.dtb \
        intel-ixp43x-kixrp435.dtb \
        intel-ixp46x-ixdp465.dtb \
+       intel-ixp42x-adi-coyote.dtb \
+       intel-ixp42x-ixdpg425.dtb \
        intel-ixp42x-iomega-nas100d.dtb \
        intel-ixp42x-dlink-dsm-g600.dtb \
        intel-ixp42x-gateworks-gw2348.dtb \

diff --git a/arch/arm/boot/dts/intel-ixp42x-adi-coyote.dts b/arch/arm/boot/dts/intel-ixp42x-adi-coyote.dts
new file mode 100644 (file)
index 0000000..44c017b
--- /dev/null
+++ b/arch/arm/boot/dts/intel-ixp42x-adi-coyote.dts
@@ -0,0 +1,110 @@
+// SPDX-License-Identifier: ISC
+/*
+ * Device Tree file for ADI Engineering Coyote platform.
+ * Derived from boardfiles written by MontaVista software.
+ * Ethernet set-up from OpenWrt.
+ */
+
+/dts-v1/;
+
+#include "intel-ixp42x.dtsi"
+#include <dt-bindings/input/input.h>
+
+/ {
+       model = "ADI Engineering Coyote reference design";
+       compatible = "adieng,coyote", "intel,ixp42x";
+       #address-cells = <1>;
+       #size-cells = <1>;
+
+       memory@0 {
+               /* CHECKME: 16 MB SDRAM minimum, maybe the Coyote actually has more */
+               device_type = "memory";
+               reg = <0x00000000 0x01000000>;
+       };
+
+       chosen {
+               bootargs = "console=ttyS0,115200n8 root=/dev/sda1 rw rootwait";
+               stdout-path = "uart1:115200n8";
+       };
+
+       aliases {
+               /* These are switched around */
+               serial0 = &uart1;
+               serial1 = &uart0;
+       };
+
+       soc {
+               bus@c4000000 {
+                       flash@0,0 {
+                               compatible = "intel,ixp4xx-flash", "cfi-flash";
+                               bank-width = <2>;
+                               /*
+                                * 32 MB of Flash in 128 0x20000 sized blocks
+                                * mapped in at CS0 and CS1
+                                */
+                               reg = <0 0x00000000 0x2000000>;
+
+                               /* Configure expansion bus to allow writes */
+                               intel,ixp4xx-eb-write-enable = <1>;
+
+                               partitions {
+                                       compatible = "redboot-fis";
+                                       /* CHECKME: guess this is Redboot FIS */
+                                       fis-index-block = <0x1ff>;
+                               };
+                       };
+               };
+
+               pci@c0000000 {
+                       status = "ok";
+
+                       /*
+                        * Taken from Coyote PCI boardfile.
+                        * We have slots (IDSEL) 1 and 2 with one assigned IRQ
+                        * each handling all IRQs.
+                        */
+                       interrupt-map =
+                       /* IDSEL 1 */
+                       <0x0800 0 0 1 &gpio0 6 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 1 is irq 6 */
+                       <0x0800 0 0 2 &gpio0 6 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 1 is irq 6 */
+                       <0x0800 0 0 3 &gpio0 6 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 1 is irq 6 */
+                       <0x0800 0 0 4 &gpio0 6 IRQ_TYPE_LEVEL_LOW>, /* INT D on slot 1 is irq 6 */
+                       /* IDSEL 2 */
+                       <0x1000 0 0 1 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 2 is irq 11 */
+                       <0x1000 0 0 2 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 2 is irq 11 */
+                       <0x1000 0 0 3 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 2 is irq 11 */
+                       <0x1000 0 0 4 &gpio0 11 IRQ_TYPE_LEVEL_LOW>; /* INT D on slot 2 is irq 11 */
+               };
+
+               /* EthB */
+               ethernet@c8009000 {
+                       status = "ok";
+                       queue-rx = <&qmgr 3>;
+                       queue-txready = <&qmgr 20>;
+                       phy-mode = "rgmii";
+                       phy-handle = <&phy5>;
+
+                       mdio {
+                               #address-cells = <1>;
+                               #size-cells = <0>;
+
+                               phy4: ethernet-phy@4 {
+                                       reg = <4>;
+                               };
+
+                               phy5: ethernet-phy@5 {
+                                       reg = <5>;
+                               };
+                       };
+               };
+
+               /* EthC */
+               ethernet@c800a000 {
+                       status = "ok";
+                       queue-rx = <&qmgr 4>;
+                       queue-txready = <&qmgr 21>;
+                       phy-mode = "rgmii";
+                       phy-handle = <&phy4>;
+               };
+       };
+};

diff --git a/arch/arm/boot/dts/intel-ixp42x-ixdpg425.dts b/arch/arm/boot/dts/intel-ixp42x-ixdpg425.dts
new file mode 100644 (file)
index 0000000..002a870
--- /dev/null
+++ b/arch/arm/boot/dts/intel-ixp42x-ixdpg425.dts
@@ -0,0 +1,125 @@
+// SPDX-License-Identifier: ISC
+/*
+ * Device Tree file for the Intel IXDPG425 reference design.
+ * Derived from boardfiles written by MontaVista software.
+ * Ethernet set-up from OpenWrt.
+ *
+ * The device has 4 x FXS RJ11 ports for analog phones for
+ * internet telephony. (Not supported yet.)
+ *
+ * The device has 9 status LEDs we do not support yet.
+ *
+ * This device is very similar to ADI engingeering Coyote.
+ */
+
+/dts-v1/;
+
+#include "intel-ixp42x.dtsi"
+#include <dt-bindings/input/input.h>
+
+/ {
+       model = "Intel IXDPG425 reference design";
+       compatible = "intel,ixdpg425", "intel,ixp42x";
+       #address-cells = <1>;
+       #size-cells = <1>;
+
+       memory@0 {
+               /* 32 MB SDRAM */
+               device_type = "memory";
+               reg = <0x00000000 0x02000000>;
+       };
+
+       chosen {
+               bootargs = "console=ttyS0,115200n8 root=/dev/sda1 rw rootwait";
+               stdout-path = "uart0:115200n8";
+       };
+
+       aliases {
+               serial0 = &uart0;
+       };
+
+       soc {
+               bus@c4000000 {
+                       flash@0,0 {
+                               compatible = "intel,ixp4xx-flash", "cfi-flash";
+                               bank-width = <2>;
+                               /*
+                                * CHECKME: the product brief says 16MB in a flash
+                                * socket.
+                                */
+                               reg = <0 0x00000000 0x1000000>;
+
+                               /* Configure expansion bus to allow writes */
+                               intel,ixp4xx-eb-write-enable = <1>;
+
+                               partitions {
+                                       compatible = "redboot-fis";
+                                       /* CHECKME: guess this is Redboot FIS */
+                                       fis-index-block = <0x7f>;
+                               };
+                       };
+               };
+
+               pci@c0000000 {
+                       status = "ok";
+
+                       /*
+                        * Taken from IXDPG425 PCI boardfile.
+                        * We have slots (IDSEL) 12, 13 and 14 with one assigned IRQ
+                        * for 12 & 13 and one for 14.
+                        */
+                       interrupt-map =
+                       /* IDSEL 12 */
+                       <0x6000 0 0 1 &gpio0 7 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 12 is irq 7 */
+                       <0x6000 0 0 2 &gpio0 7 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 12 is irq 7 */
+                       <0x6000 0 0 3 &gpio0 7 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 12 is irq 7 */
+                       <0x6000 0 0 4 &gpio0 7 IRQ_TYPE_LEVEL_LOW>, /* INT D on slot 12 is irq 7 */
+                       /* IDSEL 13 */
+                       <0x6800 0 0 1 &gpio0 7 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 13 is irq 7 */
+                       <0x6800 0 0 2 &gpio0 7 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 13 is irq 7 */
+                       <0x6800 0 0 3 &gpio0 7 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 13 is irq 7 */
+                       <0x6800 0 0 4 &gpio0 7 IRQ_TYPE_LEVEL_LOW>, /* INT D on slot 13 is irq 7 */
+                       /* IDSEL 14 */
+                       <0x7000 0 0 1 &gpio0 6 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 14 is irq 6 */
+                       <0x7000 0 0 2 &gpio0 6 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 14 is irq 6 */
+                       <0x7000 0 0 3 &gpio0 6 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 14 is irq 6 */
+                       <0x7000 0 0 4 &gpio0 6 IRQ_TYPE_LEVEL_LOW>; /* INT D on slot 14 is irq 6 */
+               };
+
+               /*
+                * CHECKME: this ethernet setup seems dubious. Photos of the board shows some kind
+                * of Realtek DSA switch on the board.
+                */
+
+               /* EthB */
+               ethernet@c8009000 {
+                       status = "ok";
+                       queue-rx = <&qmgr 3>;
+                       queue-txready = <&qmgr 20>;
+                       phy-mode = "rgmii";
+                       phy-handle = <&phy5>;
+
+                       mdio {
+                               #address-cells = <1>;
+                               #size-cells = <0>;
+
+                               phy4: ethernet-phy@4 {
+                                       reg = <4>;
+                               };
+
+                               phy5: ethernet-phy@5 {
+                                       reg = <5>;
+                               };
+                       };
+               };
+
+               /* EthC */
+               ethernet@c800a000 {
+                       status = "ok";
+                       queue-rx = <&qmgr 4>;
+                       queue-txready = <&qmgr 21>;
+                       phy-mode = "rgmii";
+                       phy-handle = <&phy4>;
+               };
+       };
+};