#define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED_DA_EXPIRATION_FLAG_SHIFT 7
#endif
u32 snd_nxt;
- u32 tx_wnd;
- u32 __reserved55;
- u32 local_adv_wnd;
+ u32 __xfrqe_bd_addr_lo;
+ u32 __xfrqe_bd_addr_hi;
+ u32 __xfrqe_data1;
#if defined(__BIG_ENDIAN)
u8 __agg_val8_th;
u8 __tx_dest;
#endif
u32 __tcp_agg_vars6;
#if defined(__BIG_ENDIAN)
- u16 __agg_misc6;
+ u16 __xfrqe_mng;
u16 __tcp_agg_vars7;
#elif defined(__LITTLE_ENDIAN)
u16 __tcp_agg_vars7;
- u16 __agg_misc6;
+ u16 __xfrqe_mng;
#endif
- u32 __agg_val10;
+ u32 __xfrqe_data0;
u32 __agg_val10_th;
#if defined(__BIG_ENDIAN)
u16 __reserved3;
#define XSTORM_FCOE_AG_CONTEXT_AGG_MISC3 (0xFF<<24)
#define XSTORM_FCOE_AG_CONTEXT_AGG_MISC3_SHIFT 24
#if defined(__BIG_ENDIAN)
- u16 agg_misc0;
+ u16 __cache_wqe_db;
u16 sq_prod;
#elif defined(__LITTLE_ENDIAN)
u16 sq_prod;
- u16 agg_misc0;
+ u16 __cache_wqe_db;
#endif
#if defined(__BIG_ENDIAN)
u8 agg_val3;
#define FCOE_TCE_TX_WR_RX_RD_CONST_RSRV1_SHIFT 5
#define FCOE_TCE_TX_WR_RX_RD_CONST_TX_SEQ_INIT (0x1<<6)
#define FCOE_TCE_TX_WR_RX_RD_CONST_TX_SEQ_INIT_SHIFT 6
-#define FCOE_TCE_TX_WR_RX_RD_CONST_RSRV2 (0x1<<7)
-#define FCOE_TCE_TX_WR_RX_RD_CONST_RSRV2_SHIFT 7
+#define FCOE_TCE_TX_WR_RX_RD_CONST_TX_COMP_TRNS (0x1<<7)
+#define FCOE_TCE_TX_WR_RX_RD_CONST_TX_COMP_TRNS_SHIFT 7
__le16 rsrv3;
__le32 verify_tx_seq;
};
#endif
#if defined(__BIG_ENDIAN)
u16 reserved_vlan_type;
- u16 params;
+ u16 vlan_params;
#define XSTORM_ETH_CONTEXT_SECTION_VLAN_ID (0xFFF<<0)
#define XSTORM_ETH_CONTEXT_SECTION_VLAN_ID_SHIFT 0
#define XSTORM_ETH_CONTEXT_SECTION_CFI (0x1<<12)
#define XSTORM_ETH_CONTEXT_SECTION_PRIORITY (0x7<<13)
#define XSTORM_ETH_CONTEXT_SECTION_PRIORITY_SHIFT 13
#elif defined(__LITTLE_ENDIAN)
- u16 params;
+ u16 vlan_params;
#define XSTORM_ETH_CONTEXT_SECTION_VLAN_ID (0xFFF<<0)
#define XSTORM_ETH_CONTEXT_SECTION_VLAN_ID_SHIFT 0
#define XSTORM_ETH_CONTEXT_SECTION_CFI (0x1<<12)