The VL805 controller can't cope with the TR Dequeue Pointer for an endpoint
being set to a Link TRB. The hardware-maintained endpoint context ends up
stuck at the address of the Link TRB, leading to erroneous ring expansion
events whenever the enqueue pointer wraps to the dequeue position.
If the search for the end of the current TD and ring cycle state lands on
a Link TRB, move to the next segment.
Link: https://github.com/raspberrypi/linux/issues/3919
[6.5.y Fixup - move downstream quirk bits further along]
Signed-off-by: Jonathan Bell <jonathan@raspberrypi.com>
if (pdev->vendor == PCI_VENDOR_ID_VIA && pdev->device == 0x3483) {
xhci->quirks |= XHCI_LPM_SUPPORT;
xhci->quirks |= XHCI_EP_CTX_BROKEN_DCS;
+ xhci->quirks |= XHCI_AVOID_DQ_ON_LINK;
}
if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA &&
} while (!cycle_found || !td_last_trb_found);
deq_found:
+ /*
+ * Quirk: the xHC does not correctly parse link TRBs if the HW Dequeue
+ * pointer is set to one. Advance to the next TRB (and next segment).
+ */
+ if (xhci->quirks & XHCI_AVOID_DQ_ON_LINK && trb_is_link(new_deq)) {
+ if (link_trb_toggles_cycle(new_deq))
+ new_cycle ^= 0x1;
+ next_trb(xhci, ep_ring, &new_seg, &new_deq);
+ }
/* Don't update the ring cycle state for the producer (us). */
addr = xhci_trb_virt_to_dma(new_seg, new_deq);
#define XHCI_ZHAOXIN_TRB_FETCH BIT_ULL(45)
#define XHCI_ZHAOXIN_HOST BIT_ULL(46)
+/* Downstream VLI fixes */
+#define XHCI_AVOID_DQ_ON_LINK BIT_ULL(56)
+
unsigned int num_active_eps;
unsigned int limit_active_eps;
struct xhci_port *hw_ports;