[PR87815]Don't generate shift sequence for load replacement in DSE when the mode...

The patch adds a check if the gap is compile-time constant.

This happens when dse decides to replace the load with previous store value.
The problem is that, shift sequence could not accept compile-time non-constant
mode operand.

gcc/

2018-11-12  Renlin Li  <renlin.li@arm.com>

	PR target/87815
	* dse.c (get_stored_val): Add check for compile-time
	constantness of gap.

gcc/testsuite/

2018-11-12  Renlin Li  <renlin.li@arm.com>

	PR target/87815
	* gcc.target/aarch64/sve/pr87815.c: New.

From-SVN: r266033

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 82da0ea..6b4a14b 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,9 @@
+2018-11-12  Renlin Li  <renlin.li@arm.com>
+
+       PR target/87815
+       * dse.c (get_stored_val): Add check for compile-time constantness
+       of gap.
+
 2018-11-12  Sudakshina Das  <sudi.das@arm.com>
 
        * config/arm/arm-cpus.in (armv8_5, sb, predres): New features.

diff --git a/gcc/dse.c b/gcc/dse.c
index cfebfa0..21d166d 100644 (file)
--- a/gcc/dse.c
+++ b/gcc/dse.c
@@ -1841,7 +1841,7 @@ get_stored_val (store_info *store_info, machine_mode read_mode,
   else
     gap = read_offset - store_info->offset;
 
-  if (maybe_ne (gap, 0))
+  if (gap.is_constant () && maybe_ne (gap, 0))
     {
       poly_int64 shift = gap * BITS_PER_UNIT;
       poly_int64 access_size = GET_MODE_SIZE (read_mode) + gap;

diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index ec4309b..64b072f 100644 (file)
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,8 @@
+2018-11-12  Renlin Li  <renlin.li@arm.com>
+
+       PR target/87815
+       * gcc.target/aarch64/sve/pr87815.c: New.
+
 2018-11-12  Sudakshina Das  <sudi.das@arm.com>
 
        * gcc.target/arm/multilib.exp: Add some -march=armv8.5-a

diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pr87815.c b/gcc/testsuite/gcc.target/aarch64/sve/pr87815.c
new file mode 100644 (file)
index 0000000..628cedb
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/sve/pr87815.c
@@ -0,0 +1,13 @@
+/* { dg-do compile { target aarch64_asm_sve_ok } } */
+/* { dg-options "-O3" } */
+int a, b, d;
+short e;
+
+void f ()
+{
+  for (int i = 0; i < 8; i++)
+    {
+      e = b >= 2 ?: a >> b;
+      d = e && b;
+    }
+}