dtb:canfd:add a dtb file for canfd
authorWilliam Qiu <william.qiu@starfivetech.com>
Tue, 30 Aug 2022 07:09:31 +0000 (15:09 +0800)
committerWilliam Qiu <william.qiu@starfivetech.com>
Tue, 30 Aug 2022 07:09:31 +0000 (15:09 +0800)
add a dtb file for canfd

Signed-off-by: William Qiu <william.qiu@starfivetech.com>
arch/riscv/boot/dts/starfive/Makefile
arch/riscv/boot/dts/starfive/jh7110-evb-can-pdm-pwmdac.dts
arch/riscv/boot/dts/starfive/jh7110-evb-canfd.dts [new file with mode: 0644]
arch/riscv/boot/dts/starfive/jh7110.dtsi

index fc946b3..5598347 100644 (file)
@@ -4,6 +4,7 @@ dtb-$(CONFIG_SOC_STARFIVE_JH7110) += jh7110-visionfive-v2.dtb   \
                                jh7110-evb.dtb                  \
                                jh7110-fpga.dtb                 \
                                jh7110-evb-can-pdm-pwmdac.dtb   \
+                               jh7110-evb-canfd.dtb            \
                                jh7110-evb-dvp-rgb2hdmi.dtb     \
                                jh7110-evb-pcie-i2s-sd.dtb      \
                                jh7110-evb-i2s-ac108.dtb        \
index 2c543cc..e947156 100644 (file)
 };
 
 &can0 {
+       syscon,can_or_canfd = <0>;
        status = "okay";
 };
 
 &can1 {
+       syscon,can_or_canfd = <0>;
        status = "okay";
 };
 
diff --git a/arch/riscv/boot/dts/starfive/jh7110-evb-canfd.dts b/arch/riscv/boot/dts/starfive/jh7110-evb-canfd.dts
new file mode 100644 (file)
index 0000000..81cd20b
--- /dev/null
@@ -0,0 +1,45 @@
+// SPDX-License-Identifier: GPL-2.0 OR MIT
+/*
+ * Copyright (C) 2022 StarFive Technology Co., Ltd.
+ * Copyright (C) 2022 William Qiu <william.qiu@starfivetech.com>
+ */
+
+/dts-v1/;
+#include "jh7110-evb.dtsi"
+
+/ {
+       model = "StarFive JH7110 EVB";
+       compatible = "starfive,jh7110-evb", "starfive,jh7110";
+};
+
+/* default sd card */
+&sdio0 {
+       clock-frequency = <102400000>;
+       max-frequency = <200000000>;
+       card-detect-delay = <300>;
+       bus-width = <4>;
+       broken-cd;
+       cap-sd-highspeed;
+       post-power-on-delay-ms = <200>;
+       pinctrl-names = "default";
+       pinctrl-0 = <&sdcard0_pins>;
+       status = "okay";
+};
+
+&usbdrd30 {
+       status = "okay";
+};
+
+&pcie1 {
+       status = "okay";
+};
+
+&can0 {
+       syscon,can_or_canfd = <1>;
+       status = "okay";
+};
+
+&can1 {
+       syscon,can_or_canfd = <1>;
+       status = "okay";
+};
\ No newline at end of file
index fc25056..6ed66a1 100755 (executable)
                                 <&rstgen RSTN_U0_CAN_CTRL_TIMER>;
                        reset-names = "rst_apb", "rst_core", "rst_timer";
                        starfive,sys-syscon = <&sys_syscon 0x10 0x3 0x8>;
-                       syscon,can_or_canfd = <0>;
                        status = "disabled";
                };
 
                                 <&rstgen RSTN_U1_CAN_CTRL_TIMER>;
                        reset-names = "rst_apb", "rst_core", "rst_timer";
                        starfive,sys-syscon = <&sys_syscon 0x88 0x12 0x40000>;
-                       syscon,can_or_canfd = <0>;
                        status = "disabled";
                };