arm64/sysreg: Convert ID_AA64FDR0_EL1 to automatic generation

Convert ID_AA64DFR0_EL1 to automatic generation as per DDI0487I.a, no
functional changes.

Signed-off-by: Mark Brown <broonie@kernel.org>
Link: https://lore.kernel.org/r/20220910163354.860255-5-broonie@kernel.org
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>

diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
index aea3ec6..943def0 100644 (file)
--- a/arch/arm64/include/asm/sysreg.h
+++ b/arch/arm64/include/asm/sysreg.h
@@ -190,7 +190,6 @@
 #define SYS_MVFR1_EL1                  sys_reg(3, 0, 0, 3, 1)
 #define SYS_MVFR2_EL1                  sys_reg(3, 0, 0, 3, 2)
 
-#define SYS_ID_AA64DFR0_EL1            sys_reg(3, 0, 0, 5, 0)
 #define SYS_ID_AA64DFR1_EL1            sys_reg(3, 0, 0, 5, 1)
 
 #define SYS_ID_AA64AFR0_EL1            sys_reg(3, 0, 0, 5, 4)
@@ -698,29 +697,6 @@
 #define ID_AA64MMFR0_EL1_PARANGE_MAX   ID_AA64MMFR0_EL1_PARANGE_48
 #endif
 
-/* id_aa64dfr0 */
-#define ID_AA64DFR0_EL1_MTPMU_SHIFT            48
-#define ID_AA64DFR0_EL1_TraceBuffer_SHIFT      44
-#define ID_AA64DFR0_EL1_TraceFilt_SHIFT                40
-#define ID_AA64DFR0_EL1_DoubleLock_SHIFT       36
-#define ID_AA64DFR0_EL1_PMSVer_SHIFT           32
-#define ID_AA64DFR0_EL1_CTX_CMPs_SHIFT         28
-#define ID_AA64DFR0_EL1_WRPs_SHIFT             20
-#define ID_AA64DFR0_EL1_BRPs_SHIFT             12
-#define ID_AA64DFR0_EL1_PMUVer_SHIFT           8
-#define ID_AA64DFR0_EL1_TraceVer_SHIFT         4
-#define ID_AA64DFR0_EL1_DebugVer_SHIFT         0
-
-#define ID_AA64DFR0_EL1_PMUVer_IMP             0x1
-#define ID_AA64DFR0_EL1_PMUVer_V3P1            0x4
-#define ID_AA64DFR0_EL1_PMUVer_V3P4            0x5
-#define ID_AA64DFR0_EL1_PMUVer_V3P5            0x6
-#define ID_AA64DFR0_EL1_PMUVer_V3P7            0x7
-#define ID_AA64DFR0_EL1_PMUVer_IMP_DEF         0xf
-
-#define ID_AA64DFR0_EL1_PMSVer_IMP             0x1
-#define ID_AA64DFR0_EL1_PMSVer_V1P1            0x2
-
 #define ID_DFR0_PERFMON_SHIFT          24
 
 #define ID_DFR0_PERFMON_8_0            0x3

diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg
index 5bccf77..e552805 100644 (file)
--- a/arch/arm64/tools/sysreg
+++ b/arch/arm64/tools/sysreg
@@ -252,6 +252,69 @@ EndEnum
 Res0   31:0
 EndSysreg
 
+Sysreg ID_AA64DFR0_EL1 3       0       0       5       0
+Enum   63:60   HPMN0
+       0b0000  UNPREDICTABLE
+       0b0001  DEF
+EndEnum
+Res0   59:56
+Enum   55:52   BRBE
+       0b0000  NI
+       0b0001  IMP
+       0b0010  BRBE_V1P1
+EndEnum
+Enum   51:48   MTPMU
+       0b0000  NI_IMPDEF
+       0b0001  IMP
+       0b1111  NI
+EndEnum
+Enum   47:44   TraceBuffer
+       0b0000  NI
+       0b0001  IMP
+EndEnum
+Enum   43:40   TraceFilt
+       0b0000  NI
+       0b0001  IMP
+EndEnum
+Enum   39:36   DoubleLock
+       0b0000  IMP
+       0b1111  NI
+EndEnum
+Enum   35:32   PMSVer
+       0b0000  NI
+       0b0001  IMP
+       0b0010  V1P1
+       0b0011  V1P2
+       0b0100  V1P3
+EndEnum
+Field  31:28   CTX_CMPs
+Res0   27:24
+Field  23:20   WRPs
+Res0   19:16
+Field  15:12   BRPs
+Enum   11:8    PMUVer
+       0b0000  NI
+       0b0001  IMP
+       0b0100  V3P1
+       0b0101  V3P4
+       0b0110  V3P5
+       0b0111  V3P7
+       0b1000  V3P8
+       0b1111  IMP_DEF
+EndEnum
+Enum   7:4     TraceVer
+       0b0000  NI
+       0b0001  IMP
+EndEnum
+Enum   3:0     DebugVer
+       0b0110  IMP
+       0b0111  VHE
+       0b1000  V8P2
+       0b1001  V8P4
+       0b1010  V8P8
+EndEnum
+EndSysreg
+
 Sysreg ID_AA64ISAR0_EL1        3       0       0       6       0
 Enum   63:60   RNDR
        0b0000  NI