spi/pxa2xx: fix incorrect SW mode chipselect setting for BayTrail LPSS SPI
authorChew, Chiau Ee <chiau.ee.chew@intel.com>
Fri, 13 Jun 2014 15:57:25 +0000 (23:57 +0800)
committerMark Brown <broonie@linaro.org>
Tue, 17 Jun 2014 14:45:52 +0000 (15:45 +0100)
It was observed that after module removal followed by insertion,
the SW mode chipselect is not properly set. Thus causing transfer
failure due to incorrect CS toggling.

Signed-off-by: Chew, Chiau Ee <chiau.ee.chew@intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Mark Brown <broonie@linaro.org>
drivers/spi/spi-pxa2xx.c

index a98df7e..fe79210 100644 (file)
@@ -118,6 +118,7 @@ static void lpss_ssp_setup(struct driver_data *drv_data)
         */
        orig = readl(drv_data->ioaddr + offset + SPI_CS_CONTROL);
 
+       /* Test SPI_CS_CONTROL_SW_MODE bit enabling */
        value = orig | SPI_CS_CONTROL_SW_MODE;
        writel(value, drv_data->ioaddr + offset + SPI_CS_CONTROL);
        value = readl(drv_data->ioaddr + offset + SPI_CS_CONTROL);
@@ -126,10 +127,13 @@ static void lpss_ssp_setup(struct driver_data *drv_data)
                goto detection_done;
        }
 
-       value &= ~SPI_CS_CONTROL_SW_MODE;
+       orig = readl(drv_data->ioaddr + offset + SPI_CS_CONTROL);
+
+       /* Test SPI_CS_CONTROL_SW_MODE bit disabling */
+       value = orig & ~SPI_CS_CONTROL_SW_MODE;
        writel(value, drv_data->ioaddr + offset + SPI_CS_CONTROL);
        value = readl(drv_data->ioaddr + offset + SPI_CS_CONTROL);
-       if (value != orig) {
+       if (value != (orig & ~SPI_CS_CONTROL_SW_MODE)) {
                offset = 0x800;
                goto detection_done;
        }