target-ppc: Introduce DFP Test Data Class

Add emulation of the PowerPC Decimal Floating Point Test Data Class
instructions dtstdc[q][.].

Signed-off-by: Tom Musta <tommusta@gmail.com>
Signed-off-by: Alexander Graf <agraf@suse.de>

diff --git a/target-ppc/dfp_helper.c b/target-ppc/dfp_helper.c
index 1816f44..fcd6fef 100644 (file)
--- a/target-ppc/dfp_helper.c
+++ b/target-ppc/dfp_helper.c
@@ -421,3 +421,31 @@ static void CMPO_PPs(struct PPC_DFP *dfp)
 
 DFP_HELPER_BF_AB(dcmpo, decNumberCompare, CMPO_PPs, 64)
 DFP_HELPER_BF_AB(dcmpoq, decNumberCompare, CMPO_PPs, 128)
+
+#define DFP_HELPER_TSTDC(op, size)                                       \
+uint32_t helper_##op(CPUPPCState *env, uint64_t *a, uint32_t dcm)        \
+{                                                                        \
+    struct PPC_DFP dfp;                                                  \
+    int match = 0;                                                       \
+                                                                         \
+    dfp_prepare_decimal##size(&dfp, a, 0, env);                          \
+                                                                         \
+    match |= (dcm & 0x20) && decNumberIsZero(&dfp.a);                    \
+    match |= (dcm & 0x10) && decNumberIsSubnormal(&dfp.a, &dfp.context); \
+    match |= (dcm & 0x08) && decNumberIsNormal(&dfp.a, &dfp.context);    \
+    match |= (dcm & 0x04) && decNumberIsInfinite(&dfp.a);                \
+    match |= (dcm & 0x02) && decNumberIsQNaN(&dfp.a);                    \
+    match |= (dcm & 0x01) && decNumberIsSNaN(&dfp.a);                    \
+                                                                         \
+    if (decNumberIsNegative(&dfp.a)) {                                   \
+        dfp.crbf = match ? 0xA : 0x8;                                    \
+    } else {                                                             \
+        dfp.crbf = match ? 0x2 : 0x0;                                    \
+    }                                                                    \
+                                                                         \
+    dfp_set_FPCC_from_CRBF(&dfp);                                        \
+    return dfp.crbf;                                                     \
+}
+
+DFP_HELPER_TSTDC(dtstdc, 64)
+DFP_HELPER_TSTDC(dtstdcq, 128)

diff --git a/target-ppc/helper.h b/target-ppc/helper.h
index 2bbae63..5a1e05e 100644 (file)
--- a/target-ppc/helper.h
+++ b/target-ppc/helper.h
@@ -628,3 +628,5 @@ DEF_HELPER_3(dcmpo, i32, env, fprp, fprp)
 DEF_HELPER_3(dcmpoq, i32, env, fprp, fprp)
 DEF_HELPER_3(dcmpu, i32, env, fprp, fprp)
 DEF_HELPER_3(dcmpuq, i32, env, fprp, fprp)
+DEF_HELPER_3(dtstdc, i32, env, fprp, i32)
+DEF_HELPER_3(dtstdcq, i32, env, fprp, i32)

diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index efd49c6..c6448e3 100644 (file)
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -8368,6 +8368,8 @@ GEN_DFP_BF_A_B(dcmpu)
 GEN_DFP_BF_A_B(dcmpuq)
 GEN_DFP_BF_A_B(dcmpo)
 GEN_DFP_BF_A_B(dcmpoq)
+GEN_DFP_BF_A_DCM(dtstdc)
+GEN_DFP_BF_A_DCM(dtstdcq)
 /***                           SPE extension                               ***/
 /* Register moves */
 
@@ -11307,6 +11309,8 @@ GEN_DFP_BF_A_B(dcmpu, 0x02, 0x14),
 GEN_DFP_BF_Ap_Bp(dcmpuq, 0x02, 0x14),
 GEN_DFP_BF_A_B(dcmpo, 0x02, 0x04),
 GEN_DFP_BF_Ap_Bp(dcmpoq, 0x02, 0x04),
+GEN_DFP_BF_A_DCM(dtstdc, 0x02, 0x06),
+GEN_DFP_BF_Ap_DCM(dtstdcq, 0x02, 0x06),
 #undef GEN_SPE
 #define GEN_SPE(name0, name1, opc2, opc3, inval0, inval1, type) \
     GEN_OPCODE_DUAL(name0##_##name1, 0x04, opc2, opc3, inval0, inval1, type, PPC_NONE)