parisc: BTLB: Initialize BTLB tables at CPU startup

Initialize the BTLB entries when starting up a CPU.
Note that BTLBs are not available on 64-bit CPUs.

Signed-off-by: Helge Deller <deller@gmx.de>

diff --git a/arch/parisc/include/asm/cache.h b/arch/parisc/include/asm/cache.h
index e23d06b..2a60d7a 100644 (file)
--- a/arch/parisc/include/asm/cache.h
+++ b/arch/parisc/include/asm/cache.h
@@ -37,6 +37,7 @@ extern int split_tlb;
 extern int dcache_stride;
 extern int icache_stride;
 extern struct pdc_cache_info cache_info;
+extern struct pdc_btlb_info btlb_info;
 void parisc_setup_cache_timing(void);
 
 #define pdtlb(sr, addr)        asm volatile("pdtlb 0(%%sr%0,%1)" \

diff --git a/arch/parisc/include/asm/processor.h b/arch/parisc/include/asm/processor.h
index d77c43d..ff6cbdb 100644 (file)
--- a/arch/parisc/include/asm/processor.h
+++ b/arch/parisc/include/asm/processor.h
@@ -310,6 +310,7 @@ extern void do_syscall_trace_exit(struct pt_regs *);
 struct seq_file;
 extern void early_trap_init(void);
 extern void collect_boot_cpu_data(void);
+extern void btlb_init_per_cpu(void);
 extern int show_cpuinfo (struct seq_file *m, void *v);
 
 /* driver code in driver/parisc */

diff --git a/arch/parisc/kernel/cache.c b/arch/parisc/kernel/cache.c
index 442109a..268d90a 100644 (file)
--- a/arch/parisc/kernel/cache.c
+++ b/arch/parisc/kernel/cache.c
@@ -58,7 +58,7 @@ int pa_serialize_tlb_flushes __ro_after_init;
 
 struct pdc_cache_info cache_info __ro_after_init;
 #ifndef CONFIG_PA20
-static struct pdc_btlb_info btlb_info __ro_after_init;
+struct pdc_btlb_info btlb_info __ro_after_init;
 #endif
 
 DEFINE_STATIC_KEY_TRUE(parisc_has_cache);
@@ -264,12 +264,6 @@ parisc_cache_init(void)
        icache_stride = CAFL_STRIDE(cache_info.ic_conf);
 #undef CAFL_STRIDE
 
-#ifndef CONFIG_PA20
-       if (pdc_btlb_info(&btlb_info) < 0) {
-               memset(&btlb_info, 0, sizeof btlb_info);
-       }
-#endif
-
        if ((boot_cpu_data.pdc.capabilities & PDC_MODEL_NVA_MASK) ==
                                                PDC_MODEL_NVA_UNSUPPORTED) {
                printk(KERN_WARNING "parisc_cache_init: Only equivalent aliasing supported!\n");

diff --git a/arch/parisc/kernel/processor.c b/arch/parisc/kernel/processor.c
index a0e2d37..1fc89fa 100644 (file)
--- a/arch/parisc/kernel/processor.c
+++ b/arch/parisc/kernel/processor.c
@@ -368,6 +368,8 @@ int init_per_cpu(int cpunum)
        /* FUTURE: Enable Performance Monitor : ccr bit 0x20 */
        init_percpu_prof(cpunum);
 
+       btlb_init_per_cpu();
+
        return ret;
 }
 

diff --git a/arch/parisc/mm/init.c b/arch/parisc/mm/init.c
index a088c24..a2a3e89 100644 (file)
--- a/arch/parisc/mm/init.c
+++ b/arch/parisc/mm/init.c
@@ -32,6 +32,7 @@
 #include <asm/sections.h>
 #include <asm/msgbuf.h>
 #include <asm/sparsemem.h>
+#include <asm/asm-offsets.h>
 
 extern int  data_start;
 extern void parisc_kernel_start(void); /* Kernel entry point in head.S */
@@ -720,6 +721,77 @@ void __init paging_init(void)
        parisc_bootmem_free();
 }
 
+static void alloc_btlb(unsigned long start, unsigned long end, int *slot,
+                       unsigned long entry_info)
+{
+       const int slot_max = btlb_info.fixed_range_info.num_comb;
+       int min_num_pages = btlb_info.min_size;
+       unsigned long size;
+
+       /* map at minimum 4 pages */
+       if (min_num_pages < 4)
+               min_num_pages = 4;
+
+       size = HUGEPAGE_SIZE;
+       while (start < end && *slot < slot_max && size >= PAGE_SIZE) {
+               /* starting address must have same alignment as size! */
+               /* if correctly aligned and fits in double size, increase */
+               if (((start & (2 * size - 1)) == 0) &&
+                   (end - start) >= (2 * size)) {
+                       size <<= 1;
+                       continue;
+               }
+               /* if current size alignment is too big, try smaller size */
+               if ((start & (size - 1)) != 0) {
+                       size >>= 1;
+                       continue;
+               }
+               if ((end - start) >= size) {
+                       if ((size >> PAGE_SHIFT) >= min_num_pages)
+                               pdc_btlb_insert(start >> PAGE_SHIFT, __pa(start) >> PAGE_SHIFT,
+                                       size >> PAGE_SHIFT, entry_info, *slot);
+                       (*slot)++;
+                       start += size;
+                       continue;
+               }
+               size /= 2;
+               continue;
+       }
+}
+
+void btlb_init_per_cpu(void)
+{
+       unsigned long s, t, e;
+       int slot;
+
+       /* BTLBs are not available on 64-bit CPUs */
+       if (IS_ENABLED(CONFIG_PA20))
+               return;
+       else if (pdc_btlb_info(&btlb_info) < 0) {
+               memset(&btlb_info, 0, sizeof btlb_info);
+       }
+
+       /* insert BLTLBs for code and data segments */
+       s = (uintptr_t) dereference_function_descriptor(&_stext);
+       e = (uintptr_t) dereference_function_descriptor(&_etext);
+       t = (uintptr_t) dereference_function_descriptor(&_sdata);
+       BUG_ON(t != e);
+
+       /* code segments */
+       slot = 0;
+       alloc_btlb(s, e, &slot, 0x13800000);
+
+       /* sanity check */
+       t = (uintptr_t) dereference_function_descriptor(&_edata);
+       e = (uintptr_t) dereference_function_descriptor(&__bss_start);
+       BUG_ON(t != e);
+
+       /* data segments */
+       s = (uintptr_t) dereference_function_descriptor(&_sdata);
+       e = (uintptr_t) dereference_function_descriptor(&__bss_stop);
+       alloc_btlb(s, e, &slot, 0x11800000);
+}
+
 #ifdef CONFIG_PA20
 
 /*