}
}
+static bool
+si_spm_init_bo(struct si_context *sctx)
+{
+ struct radeon_winsys *ws = sctx->ws;
+ uint64_t size = 32 * 1024 * 1024; /* Default to 32MB. */
+
+ sctx->spm_trace.buffer_size = size;
+ sctx->spm_trace.sample_interval = 4096; /* Default to 4096 clk. */
+
+ sctx->spm_trace.bo = ws->buffer_create(
+ ws, size, 4096,
+ RADEON_DOMAIN_VRAM,
+ RADEON_FLAG_NO_INTERPROCESS_SHARING |
+ RADEON_FLAG_GTT_WC |
+ RADEON_FLAG_NO_SUBALLOC);
+
+ return sctx->spm_trace.bo != NULL;
+}
+
+
static void
si_emit_spm_counters(struct si_context *sctx, struct radeon_cmdbuf *cs)
{
if (!ac_init_spm(info, pc, ARRAY_SIZE(spm_counters), spm_counters, &sctx->spm_trace))
return false;
+ if (!si_spm_init_bo(sctx))
+ return false;
+
return true;
}
void
si_spm_finish(struct si_context *sctx)
{
+ struct pb_buffer *bo = sctx->spm_trace.bo;
+ radeon_bo_reference(sctx->screen->ws, &bo, NULL);
+
ac_destroy_spm(&sctx->spm_trace);
}
sctx->thread_trace->bo,
RADEON_USAGE_READWRITE,
RADEON_DOMAIN_VRAM);
+ ws->cs_add_buffer(cs,
+ sctx->spm_trace.bo,
+ RADEON_USAGE_READWRITE,
+ RADEON_DOMAIN_VRAM);
si_cp_dma_wait_for_idle(sctx, cs);
RADEON_USAGE_READWRITE,
RADEON_DOMAIN_VRAM);
+ ws->cs_add_buffer(cs,
+ sctx->spm_trace.bo,
+ RADEON_USAGE_READWRITE,
+ RADEON_DOMAIN_VRAM);
+
si_cp_dma_wait_for_idle(sctx, cs);
/* Make sure to wait-for-idle before stopping SQTT. */
/* Wait for SQTT to finish and read back the bo */
if (sctx->ws->fence_wait(sctx->ws, sctx->last_sqtt_fence, PIPE_TIMEOUT_INFINITE) &&
si_get_thread_trace(sctx, &thread_trace)) {
- ac_dump_rgp_capture(&sctx->screen->info, &thread_trace, NULL);
+ ac_dump_rgp_capture(&sctx->screen->info, &thread_trace, &sctx->spm_trace);
} else {
fprintf(stderr, "Failed to read the trace\n");
}