Revert "drm/i915/tgl: Implement Wa_1406941453"
authorChris Wilson <chris@chris-wilson.co.uk>
Fri, 20 Sep 2019 08:12:54 +0000 (09:12 +0100)
committerChris Wilson <chris@chris-wilson.co.uk>
Fri, 20 Sep 2019 10:59:33 +0000 (11:59 +0100)
Our sanitychecks indicate that while this register is context
saved/restore, the HW does not preserve this bit within the register --
it likely doesn't exist, or one of those mythical bits that the
architects insist does something despite all appearances to the
contrary.

For reference, SAMPLER_MODE is already in i915_reg.h as
GEN10_SAMPLER_MODE and is being setup in icl_ctx_workarounds_init() as
opposed to the chosen location here of rcs_engine_wa_init).

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=111754
Fixes: 7f0cc34b5349 ("drm/i915/tgl: Implement Wa_1406941453")
Testcase: igt/i915_selftest/live_workarounds
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Cc: Stuart Summers <stuart.summers@intel.com>
Cc: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
Cc: Jani Nikula <jani.nikula@linux.intel.com>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Acked-by: Lucas De Marchi <lucas.demarchi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190920081254.18389-1-chris@chris-wilson.co.uk
drivers/gpu/drm/i915/gt/intel_workarounds.c
drivers/gpu/drm/i915/i915_reg.h

index 25ae608..ba65e50 100644 (file)
@@ -1260,13 +1260,6 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
 {
        struct drm_i915_private *i915 = engine->i915;
 
-       if (IS_GEN(i915, 12)) {
-               /* Wa_1406941453:tgl */
-               wa_masked_en(wal,
-                            SAMPLER_MODE,
-                            SAMPLER_ENABLE_SMALL_PL);
-       }
-
        if (IS_GEN(i915, 11)) {
                /* This is not an Wa. Enable for better image quality */
                wa_masked_en(wal,
index 5e3a617..f8f52ae 100644 (file)
@@ -8965,9 +8965,6 @@ enum {
 #define   GEN9_DG_MIRROR_FIX_ENABLE    (1 << 5)
 #define   GEN9_CCS_TLB_PREFETCH_ENABLE (1 << 3)
 
-#define SAMPLER_MODE                   _MMIO(0xe18c)
-#define   SAMPLER_ENABLE_SMALL_PL      (1 << 15)
-
 #define GEN8_ROW_CHICKEN               _MMIO(0xe4f0)
 #define   FLOW_CONTROL_ENABLE          (1 << 15)
 #define   PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE        (1 << 8)