/* XXX: enable it in all cases */
env->cpuid_features |= CPUID_APIC;
}
- register_savevm("cpu", 0, 3, cpu_save, cpu_load, env);
+ register_savevm("cpu", i, 3, cpu_save, cpu_load, env);
qemu_register_reset(main_cpu_reset, env);
if (pci_enabled) {
apic_init(env);
for(i = 0; i < MAX_SERIAL_PORTS; i++) {
if (serial_hds[i]) {
- serial_init(serial_io[i], serial_irq[i], serial_hds[i]);
+ serial_init(&pic_set_irq_new, isa_pic,
+ serial_io[i], serial_irq[i], serial_hds[i]);
}
}
isa_pic = pic_init(pic_irq_request, NULL);
/* XXX: use Mac Serial port */
- serial_init(0x3f8, 4, serial_hds[0]);
+ serial_init(&pic_set_irq_new, isa_pic, 0x3f8, 4, serial_hds[0]);
for(i = 0; i < nb_nics; i++) {
pci_ne2000_init(pci_bus, &nd_table[i]);
isa_pic = pic_init(pic_irq_request, NULL);
/* XXX: use Mac Serial port */
- serial_init(0x3f8, 4, serial_hds[0]);
+ serial_init(&pic_set_irq_new, isa_pic, 0x3f8, 4, serial_hds[0]);
for(i = 0; i < nb_nics; i++) {
pci_ne2000_init(pci_bus, &nd_table[i]);
/* NOTE: this hidden state is necessary for tx irq generation as
it can be reset while reading iir */
int thr_ipending;
+ SetIRQFunc *set_irq;
+ void *irq_opaque;
int irq;
CharDriverState *chr;
int last_break_enable;
+ target_ulong base;
+ int it_shift;
};
static void serial_update_irq(SerialState *s)
s->iir = UART_IIR_NO_INT;
}
if (s->iir != UART_IIR_NO_INT) {
- pic_set_irq(s->irq, 1);
+ s->set_irq(s->irq_opaque, s->irq, 1);
} else {
- pic_set_irq(s->irq, 0);
+ s->set_irq(s->irq_opaque, s->irq, 0);
}
}
}
/* If fd is zero, it means that the serial device uses the console */
-SerialState *serial_init(int base, int irq, CharDriverState *chr)
+SerialState *serial_init(SetIRQFunc *set_irq, void *opaque,
+ int base, int irq, CharDriverState *chr)
{
SerialState *s;
s = qemu_mallocz(sizeof(SerialState));
if (!s)
return NULL;
+ s->set_irq = set_irq;
+ s->irq_opaque = opaque;
s->irq = irq;
s->lsr = UART_LSR_TEMT | UART_LSR_THRE;
s->iir = UART_IIR_NO_INT;
qemu_chr_add_event_handler(chr, serial_event);
return s;
}
+
+/* Memory mapped interface */
+static uint32_t serial_mm_readb (void *opaque, target_phys_addr_t addr)
+{
+ SerialState *s = opaque;
+
+ return serial_ioport_read(s, (addr - s->base) >> s->it_shift) & 0xFF;
+}
+
+static void serial_mm_writeb (void *opaque,
+ target_phys_addr_t addr, uint32_t value)
+{
+ SerialState *s = opaque;
+
+ serial_ioport_write(s, (addr - s->base) >> s->it_shift, value & 0xFF);
+}
+
+static uint32_t serial_mm_readw (void *opaque, target_phys_addr_t addr)
+{
+ SerialState *s = opaque;
+
+ return serial_ioport_read(s, (addr - s->base) >> s->it_shift) & 0xFFFF;
+}
+
+static void serial_mm_writew (void *opaque,
+ target_phys_addr_t addr, uint32_t value)
+{
+ SerialState *s = opaque;
+
+ serial_ioport_write(s, (addr - s->base) >> s->it_shift, value & 0xFFFF);
+}
+
+static uint32_t serial_mm_readl (void *opaque, target_phys_addr_t addr)
+{
+ SerialState *s = opaque;
+
+ return serial_ioport_read(s, (addr - s->base) >> s->it_shift);
+}
+
+static void serial_mm_writel (void *opaque,
+ target_phys_addr_t addr, uint32_t value)
+{
+ SerialState *s = opaque;
+
+ serial_ioport_write(s, (addr - s->base) >> s->it_shift, value);
+}
+
+static CPUReadMemoryFunc *serial_mm_read[] = {
+ &serial_mm_readb,
+ &serial_mm_readw,
+ &serial_mm_readl,
+};
+
+static CPUWriteMemoryFunc *serial_mm_write[] = {
+ &serial_mm_writeb,
+ &serial_mm_writew,
+ &serial_mm_writel,
+};
+
+SerialState *serial_mm_init (SetIRQFunc *set_irq, void *opaque,
+ target_ulong base, int it_shift,
+ int irq, CharDriverState *chr)
+{
+ SerialState *s;
+ int s_io_memory;
+
+ s = qemu_mallocz(sizeof(SerialState));
+ if (!s)
+ return NULL;
+ s->set_irq = set_irq;
+ s->irq_opaque = opaque;
+ s->irq = irq;
+ s->lsr = UART_LSR_TEMT | UART_LSR_THRE;
+ s->iir = UART_IIR_NO_INT;
+ s->base = base;
+ s->it_shift = it_shift;
+
+ register_savevm("serial", base, 1, serial_save, serial_load, s);
+
+ s_io_memory = cpu_register_io_memory(0, serial_mm_read,
+ serial_mm_write, s);
+ cpu_register_physical_memory(base, 8 << it_shift, s_io_memory);
+ s->chr = chr;
+ qemu_chr_add_read_handler(chr, serial_can_receive1, serial_receive1, s);
+ qemu_chr_add_event_handler(chr, serial_event);
+ return s;
+}