MIPS: Netlogic: XLP2xx update for I2C controller

XLP2xx has a new I2C controller which has 4 buses connected to
it. Update the IO offset and IRQ mapping code to reflect this.

Signed-off-by: Ganesan Ramalingam <ganesanr@broadcom.com>
Signed-off-by: Jayachandran C <jchandra@broadcom.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/5707/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

diff --git a/arch/mips/include/asm/netlogic/xlp-hal/iomap.h b/arch/mips/include/asm/netlogic/xlp-hal/iomap.h
index 9fac46f..61c84de 100644 (file)
--- a/arch/mips/include/asm/netlogic/xlp-hal/iomap.h
+++ b/arch/mips/include/asm/netlogic/xlp-hal/iomap.h
@@ -88,6 +88,9 @@
 #define XLP_IO_I2C0_OFFSET(node)       XLP_HDR_OFFSET(node, 0, 6, 2)
 #define XLP_IO_I2C1_OFFSET(node)       XLP_HDR_OFFSET(node, 0, 6, 3)
 #define XLP_IO_GPIO_OFFSET(node)       XLP_HDR_OFFSET(node, 0, 6, 4)
+/* on 2XX, all I2C busses are on the same block */
+#define XLP2XX_IO_I2C_OFFSET(node)     XLP_HDR_OFFSET(node, 0, 6, 7)
+
 /* system management */
 #define XLP_IO_SYS_OFFSET(node)                XLP_HDR_OFFSET(node, 0, 6, 5)
 #define XLP_IO_JTAG_OFFSET(node)       XLP_HDR_OFFSET(node, 0, 6, 6)

diff --git a/arch/mips/include/asm/netlogic/xlp-hal/xlp.h b/arch/mips/include/asm/netlogic/xlp-hal/xlp.h
index 7a4a514..4950ea5 100644 (file)
--- a/arch/mips/include/asm/netlogic/xlp-hal/xlp.h
+++ b/arch/mips/include/asm/netlogic/xlp-hal/xlp.h
@@ -50,6 +50,8 @@
 #define PIC_MMC_IRQ                    29
 #define PIC_I2C_0_IRQ                  30
 #define PIC_I2C_1_IRQ                  31
+#define PIC_I2C_2_IRQ                  32
+#define PIC_I2C_3_IRQ                  33
 
 #ifndef __ASSEMBLY__
 

diff --git a/arch/mips/netlogic/xlp/nlm_hal.c b/arch/mips/netlogic/xlp/nlm_hal.c
index 22e2e02..04adb75 100644 (file)
--- a/arch/mips/netlogic/xlp/nlm_hal.c
+++ b/arch/mips/netlogic/xlp/nlm_hal.c
@@ -93,11 +93,14 @@ int nlm_irq_to_irt(int irq)
        case PIC_MMC_IRQ:
                devoff = XLP_IO_SD_OFFSET(0);
                break;
-       case PIC_I2C_0_IRQ:
-               devoff = XLP_IO_I2C0_OFFSET(0);
-               break;
+       case PIC_I2C_0_IRQ:     /* I2C will be fixed up */
        case PIC_I2C_1_IRQ:
-               devoff = XLP_IO_I2C1_OFFSET(0);
+       case PIC_I2C_2_IRQ:
+       case PIC_I2C_3_IRQ:
+               if (cpu_is_xlpii())
+                       devoff = XLP2XX_IO_I2C_OFFSET(0);
+               else
+                       devoff = XLP_IO_I2C0_OFFSET(0);
                break;
        default:
                devoff = 0;
@@ -107,9 +110,15 @@ int nlm_irq_to_irt(int irq)
        if (devoff != 0) {
                pcibase = nlm_pcicfg_base(devoff);
                irt = nlm_read_reg(pcibase, XLP_PCI_IRTINFO_REG) & 0xffff;
-               /* HW bug, I2C 1 irt entry is off by one */
-               if (irq == PIC_I2C_1_IRQ)
-                       irt = irt + 1;
+               /* HW weirdness, I2C IRT entry has to be fixed up */
+               switch (irq) {
+               case PIC_I2C_1_IRQ:
+                       irt = irt + 1; break;
+               case PIC_I2C_2_IRQ:
+                       irt = irt + 2; break;
+               case PIC_I2C_3_IRQ:
+                       irt = irt + 3; break;
+               }
        } else if (irq >= PIC_PCIE_LINK_0_IRQ && irq <= PIC_PCIE_LINK_3_IRQ) {
                /* HW bug, PCI IRT entries are bad on early silicon, fix */
                irt = PIC_IRT_PCIE_LINK_INDEX(irq - PIC_PCIE_LINK_0_IRQ);