Address div/mod CR feedback

Commit migrated from https://github.com/dotnet/coreclr/commit/56c425835dcb35bbdaf1f7639a6580ea4a8215e9

diff --git a/src/coreclr/src/jit/codegenarm64.cpp b/src/coreclr/src/jit/codegenarm64.cpp
index e02e922..2f8879a 100644 (file)
--- a/src/coreclr/src/jit/codegenarm64.cpp
+++ b/src/coreclr/src/jit/codegenarm64.cpp
@@ -2460,8 +2460,6 @@ CodeGen::genCodeForTreeNode(GenTreePtr treeNode)
             GenTreePtr divisorOp = treeNode->gtGetOp2();
             emitAttr   size      = EA_ATTR(genTypeSize(genActualType(treeNode->TypeGet())));
 
-            // TODO-ARM64-CQ: Optimize a divide by power of 2 as we do for AMD64
-
             if (divisorOp->IsIntegralConst(0))
             {
                 // We unconditionally throw a divide by zero exception

diff --git a/src/coreclr/src/jit/lower.cpp b/src/coreclr/src/jit/lower.cpp
index 26f3a53..e54130e 100755 (executable)
--- a/src/coreclr/src/jit/lower.cpp
+++ b/src/coreclr/src/jit/lower.cpp
@@ -4030,6 +4030,7 @@ void Lowering::LowerUnsignedDivOrMod(GenTree* tree)
 //
 // Arguments:
 //    pTree:   pointer to the parent node's link to the node we care about
+//    data:    fgWalkData which is used to get info about parents and fixup call args
 
 void Lowering::LowerSignedDivOrMod(GenTreePtr* ppTree, Compiler::fgWalkData* data)
 {