[Hexagon][llvm-objcopy] Add missing check for SHN_HEXAGON_SCOMMON_1

Differential Revision: https://reviews.llvm.org/D82484

diff --git a/llvm/test/tools/llvm-objcopy/ELF/common-symbol.test b/llvm/test/tools/llvm-objcopy/ELF/common-symbol.test
index 98e73d2..4a4c295 100644 (file)
--- a/llvm/test/tools/llvm-objcopy/ELF/common-symbol.test
+++ b/llvm/test/tools/llvm-objcopy/ELF/common-symbol.test
@@ -11,10 +11,14 @@ FileHeader:
 Symbols:
   - Name:     test
     Index:    SHN_COMMON
+    Value:    0x1233
+    Binding:  STB_GLOBAL
+  - Name:     test1
+    Index:    SHN_HEXAGON_SCOMMON
     Value:    0x1234
     Binding:  STB_GLOBAL
   - Name:     test2
-    Index:    SHN_HEXAGON_SCOMMON
+    Index:    SHN_HEXAGON_SCOMMON_1
     Value:    0x1235
     Binding:  STB_GLOBAL
   - Name:     test3
@@ -42,7 +46,7 @@ Symbols:
 #CHECK-NEXT:  }
 #CHECK-NEXT:  Symbol {
 #CHECK-NEXT:    Name: test
-#CHECK-NEXT:    Value: 0x1234
+#CHECK-NEXT:    Value: 0x1233
 #CHECK-NEXT:    Size: 0
 #CHECK-NEXT:    Binding: Global (0x1)
 #CHECK-NEXT:    Type: None (0x0)
@@ -50,13 +54,22 @@ Symbols:
 #CHECK-NEXT:    Section: Common (0xFFF2)
 #CHECK-NEXT:  }
 #CHECK-NEXT:  Symbol {
+#CHECK-NEXT:    Name: test1
+#CHECK-NEXT:    Value: 0x1234
+#CHECK-NEXT:    Size: 0
+#CHECK-NEXT:    Binding: Global (0x1)
+#CHECK-NEXT:    Type: None (0x0)
+#CHECK-NEXT:    Other: 0
+#CHECK-NEXT:    Section: Processor Specific (0xFF00)
+#CHECK-NEXT:  }
+#CHECK-NEXT:  Symbol {
 #CHECK-NEXT:    Name: test2
 #CHECK-NEXT:    Value: 0x1235
 #CHECK-NEXT:    Size: 0
 #CHECK-NEXT:    Binding: Global (0x1)
 #CHECK-NEXT:    Type: None (0x0)
 #CHECK-NEXT:    Other: 0
-#CHECK-NEXT:    Section: Processor Specific (0xFF00)
+#CHECK-NEXT:    Section: Processor Specific (0xFF01)
 #CHECK-NEXT:  }
 #CHECK-NEXT:  Symbol {
 #CHECK-NEXT:    Name: test3

diff --git a/llvm/tools/llvm-objcopy/ELF/Object.cpp b/llvm/tools/llvm-objcopy/ELF/Object.cpp
index 8bb4bbb..8e8c5fe 100644 (file)
--- a/llvm/tools/llvm-objcopy/ELF/Object.cpp
+++ b/llvm/tools/llvm-objcopy/ELF/Object.cpp
@@ -608,6 +608,7 @@ static bool isValidReservedSectionIndex(uint16_t Index, uint16_t Machine) {
   if (Machine == EM_HEXAGON) {
     switch (Index) {
     case SHN_HEXAGON_SCOMMON:
+    case SHN_HEXAGON_SCOMMON_1:
     case SHN_HEXAGON_SCOMMON_2:
     case SHN_HEXAGON_SCOMMON_4:
     case SHN_HEXAGON_SCOMMON_8: