(define_cpu_unit "ixum_addsub_agen" "rm7000_other")
;; Integer execution unit (F-Pipe).
-(define_cpu_unit "ixuf_addsub" "rm7000_other")
-(define_cpu_unit "ixuf_branch" "rm7000_other")
-(define_cpu_unit "ixuf_mpydiv" "rm7000_other")
+(define_cpu_unit "ixuf_addsub" "rm7000_other")
+(define_cpu_unit "ixuf_branch" "rm7000_other")
+(define_cpu_unit "ixuf_mpydiv" "rm7000_other")
(define_cpu_unit "ixuf_mpydiv_iter" "rm7000_idiv")
;; Floating-point unit (F-Pipe).
-(define_cpu_unit "fxuf_add" "rm7000_other")
-(define_cpu_unit "fxuf_mpy" "rm7000_other")
+(define_cpu_unit "fxuf_add" "rm7000_other")
+(define_cpu_unit "fxuf_mpy" "rm7000_other")
(define_cpu_unit "fxuf_mpy_iter" "rm7000_fdiv")
(define_cpu_unit "fxuf_divsqrt" "rm7000_other")
(define_cpu_unit "fxuf_divsqrt_iter" "rm7000_fdiv")
(exclusion_set "ixuf_addsub"
"ixuf_branch,ixuf_mpydiv,fxuf_add,fxuf_mpy,fxuf_divsqrt")
-(exclusion_set "ixuf_branch" "ixuf_mpydiv,fxuf_add,fxuf_mpy,fxuf_divsqrt")
-(exclusion_set "ixuf_mpydiv" "fxuf_add,fxuf_mpy,fxuf_divsqrt")
-(exclusion_set "fxuf_add" "fxuf_mpy,fxuf_divsqrt")
-(exclusion_set "fxuf_mpy" "fxuf_divsqrt")
+(exclusion_set "ixuf_branch" "ixuf_mpydiv,fxuf_add,fxuf_mpy,fxuf_divsqrt")
+(exclusion_set "ixuf_mpydiv" "fxuf_add,fxuf_mpy,fxuf_divsqrt")
+(exclusion_set "fxuf_add" "fxuf_mpy,fxuf_divsqrt")
+(exclusion_set "fxuf_mpy" "fxuf_divsqrt")
;; After branch any insn cannot be issued.
(absence_set "rm7_iss0,rm7_iss1" "ixuf_branch")
;; Define reservations for unit name mnemonics or combinations.
;;
-(define_reservation "rm7_iss" "rm7_iss0|rm7_iss1")
+(define_reservation "rm7_iss" "rm7_iss0|rm7_iss1")
(define_reservation "rm7_single_dispatch" "rm7_iss0+rm7_iss1")
(define_reservation "rm7_iaddsub" "rm7_iss+(ixum_addsub_agen|ixuf_addsub)")
-(define_reservation "rm7_imem" "rm7_iss+ixum_addsub_agen")
-(define_reservation "rm7_impydiv" "rm7_iss+ixuf_mpydiv")
-(define_reservation "rm7_impydiv_iter" "ixuf_mpydiv_iter")
-(define_reservation "rm7_branch" "rm7_iss+ixuf_branch")
+(define_reservation "rm7_imem" "rm7_iss+ixum_addsub_agen")
+(define_reservation "rm7_impydiv" "rm7_iss+ixuf_mpydiv")
+(define_reservation "rm7_impydiv_iter" "ixuf_mpydiv_iter")
+(define_reservation "rm7_branch" "rm7_iss+ixuf_branch")
(define_reservation "rm7_fpadd" "rm7_iss+fxuf_add")
(define_reservation "rm7_fpmpy" "rm7_iss+fxuf_mpy")
;;
(define_insn_reservation "rm7_int_other" 1
- (and (eq_attr "cpu" "r7000")
- (eq_attr "type" "arith,shift,slt,clz,const,condmove,nop,trap"))
- "rm7_iaddsub")
-
-(define_insn_reservation "rm7_ld" 2 (and (eq_attr "cpu" "r7000")
- (eq_attr "type" "load,fpload,fpidxload"))
- "rm7_imem")
-
-(define_insn_reservation "rm7_st" 1 (and (eq_attr "cpu" "r7000")
- (eq_attr "type" "store,fpstore,fpidxstore"))
- "rm7_imem")
-
-(define_insn_reservation "rm7_idiv_si" 36 (and (eq_attr "cpu" "r7000")
- (and (eq_attr "type" "idiv")
- (eq_attr "mode" "SI")))
- "rm7_impydiv+(rm7_impydiv_iter*36)")
-
-(define_insn_reservation "rm7_idiv_di" 68 (and (eq_attr "cpu" "r7000")
- (and (eq_attr "type" "idiv")
- (eq_attr "mode" "DI")))
- "rm7_impydiv+(rm7_impydiv_iter*68)")
+ (and (eq_attr "cpu" "r7000")
+ (eq_attr "type" "arith,shift,slt,clz,const,condmove,nop,trap"))
+ "rm7_iaddsub")
+
+(define_insn_reservation "rm7_ld" 2
+ (and (eq_attr "cpu" "r7000")
+ (eq_attr "type" "load,fpload,fpidxload"))
+ "rm7_imem")
+
+(define_insn_reservation "rm7_st" 1
+ (and (eq_attr "cpu" "r7000")
+ (eq_attr "type" "store,fpstore,fpidxstore"))
+ "rm7_imem")
+
+(define_insn_reservation "rm7_idiv_si" 36
+ (and (eq_attr "cpu" "r7000")
+ (and (eq_attr "type" "idiv")
+ (eq_attr "mode" "SI")))
+ "rm7_impydiv+(rm7_impydiv_iter*36)")
+
+(define_insn_reservation "rm7_idiv_di" 68
+ (and (eq_attr "cpu" "r7000")
+ (and (eq_attr "type" "idiv")
+ (eq_attr "mode" "DI")))
+ "rm7_impydiv+(rm7_impydiv_iter*68)")
(define_insn_reservation "rm7_impy_si_mult" 5
- (and (eq_attr "cpu" "r7000")
- (and (eq_attr "type" "imul,imul3,imadd")
- (and (eq_attr "mode" "SI")
- (match_operand 0 "hilo_operand"))))
- "rm7_impydiv+(rm7_impydiv_iter*3)")
+ (and (eq_attr "cpu" "r7000")
+ (and (eq_attr "type" "imul,imul3,imadd")
+ (and (eq_attr "mode" "SI")
+ (match_operand 0 "hilo_operand"))))
+ "rm7_impydiv+(rm7_impydiv_iter*3)")
;; There are an additional 2 stall cycles.
(define_insn_reservation "rm7_impy_si_mul" 2
- (and (eq_attr "cpu" "r7000")
- (and (eq_attr "type" "imul,imul3,imadd")
- (and (eq_attr "mode" "SI")
- (not (match_operand 0 "hilo_operand")))))
- "rm7_impydiv")
-
-(define_insn_reservation "rm7_impy_di" 9 (and (eq_attr "cpu" "r7000")
- (and (eq_attr "type" "imul,imul3")
- (eq_attr "mode" "DI")))
- "rm7_impydiv+(rm7_impydiv_iter*8)")
+ (and (eq_attr "cpu" "r7000")
+ (and (eq_attr "type" "imul,imul3,imadd")
+ (and (eq_attr "mode" "SI")
+ (not (match_operand 0 "hilo_operand")))))
+ "rm7_impydiv")
+
+(define_insn_reservation "rm7_impy_di" 9
+ (and (eq_attr "cpu" "r7000")
+ (and (eq_attr "type" "imul,imul3")
+ (eq_attr "mode" "DI")))
+ "rm7_impydiv+(rm7_impydiv_iter*8)")
;; Move to/from HI/LO.
(define_insn_reservation "rm7_mthilo" 3
- (and (eq_attr "cpu" "r7000")
- (eq_attr "type" "mthilo"))
- "rm7_impydiv")
+ (and (eq_attr "cpu" "r7000")
+ (eq_attr "type" "mthilo"))
+ "rm7_impydiv")
(define_insn_reservation "rm7_mfhilo" 1
- (and (eq_attr "cpu" "r7000")
- (eq_attr "type" "mfhilo"))
- "rm7_impydiv")
+ (and (eq_attr "cpu" "r7000")
+ (eq_attr "type" "mfhilo"))
+ "rm7_impydiv")
;; Move to/from fp coprocessor.
-(define_insn_reservation "rm7_ixfer" 2 (and (eq_attr "cpu" "r7000")
- (eq_attr "type" "xfer"))
- "rm7_iaddsub")
+(define_insn_reservation "rm7_ixfer" 2
+ (and (eq_attr "cpu" "r7000")
+ (eq_attr "type" "xfer"))
+ "rm7_iaddsub")
-(define_insn_reservation "rm7_ibr" 3 (and (eq_attr "cpu" "r7000")
- (eq_attr "type" "branch,jump,call"))
- "rm7_branch")
+(define_insn_reservation "rm7_ibr" 3
+ (and (eq_attr "cpu" "r7000")
+ (eq_attr "type" "branch,jump,call"))
+ "rm7_branch")
;;
;; Describe instruction reservations for the floating-point operations.
;;
(define_insn_reservation "rm7_fp_quick" 4
- (and (eq_attr "cpu" "r7000")
- (eq_attr "type" "fneg,fcmp,fabs,fmove"))
- "rm7_fpadd")
+ (and (eq_attr "cpu" "r7000")
+ (eq_attr "type" "fneg,fcmp,fabs,fmove"))
+ "rm7_fpadd")
(define_insn_reservation "rm7_fp_other" 4
- (and (eq_attr "cpu" "r7000")
- (eq_attr "type" "fadd"))
- "rm7_fpadd")
+ (and (eq_attr "cpu" "r7000")
+ (eq_attr "type" "fadd"))
+ "rm7_fpadd")
(define_insn_reservation "rm7_fp_cvt" 4
- (and (eq_attr "cpu" "r7000")
- (eq_attr "type" "fcvt"))
- "rm7_fpadd")
+ (and (eq_attr "cpu" "r7000")
+ (eq_attr "type" "fcvt"))
+ "rm7_fpadd")
(define_insn_reservation "rm7_fp_divsqrt_df" 36
- (and (eq_attr "cpu" "r7000")
- (and (eq_attr "type" "fdiv,frdiv,fsqrt")
- (eq_attr "mode" "DF")))
- "rm7_fpdivsqr+(rm7_fpdivsqr_iter*36)")
+ (and (eq_attr "cpu" "r7000")
+ (and (eq_attr "type" "fdiv,frdiv,fsqrt")
+ (eq_attr "mode" "DF")))
+ "rm7_fpdivsqr+(rm7_fpdivsqr_iter*36)")
(define_insn_reservation "rm7_fp_divsqrt_sf" 21
- (and (eq_attr "cpu" "r7000")
- (and (eq_attr "type" "fdiv,frdiv,fsqrt")
- (eq_attr "mode" "SF")))
- "rm7_fpdivsqr+(rm7_fpdivsqr_iter*21)")
+ (and (eq_attr "cpu" "r7000")
+ (and (eq_attr "type" "fdiv,frdiv,fsqrt")
+ (eq_attr "mode" "SF")))
+ "rm7_fpdivsqr+(rm7_fpdivsqr_iter*21)")
(define_insn_reservation "rm7_fp_rsqrt_df" 68
- (and (eq_attr "cpu" "r7000")
- (and (eq_attr "type" "frsqrt")
- (eq_attr "mode" "DF")))
- "rm7_fpdivsqr+(rm7_fpdivsqr_iter*68)")
+ (and (eq_attr "cpu" "r7000")
+ (and (eq_attr "type" "frsqrt")
+ (eq_attr "mode" "DF")))
+ "rm7_fpdivsqr+(rm7_fpdivsqr_iter*68)")
(define_insn_reservation "rm7_fp_rsqrt_sf" 38
- (and (eq_attr "cpu" "r7000")
- (and (eq_attr "type" "frsqrt")
- (eq_attr "mode" "SF")))
- "rm7_fpdivsqr+(rm7_fpdivsqr_iter*38)")
+ (and (eq_attr "cpu" "r7000")
+ (and (eq_attr "type" "frsqrt")
+ (eq_attr "mode" "SF")))
+ "rm7_fpdivsqr+(rm7_fpdivsqr_iter*38)")
(define_insn_reservation "rm7_fp_mpy_sf" 4
- (and (eq_attr "cpu" "r7000")
- (and (eq_attr "type" "fmul,fmadd")
- (eq_attr "mode" "SF")))
- "rm7_fpmpy+rm7_fpmpy_iter")
+ (and (eq_attr "cpu" "r7000")
+ (and (eq_attr "type" "fmul,fmadd")
+ (eq_attr "mode" "SF")))
+ "rm7_fpmpy+rm7_fpmpy_iter")
(define_insn_reservation "rm7_fp_mpy_df" 5
- (and (eq_attr "cpu" "r7000")
- (and (eq_attr "type" "fmul,fmadd")
- (eq_attr "mode" "DF")))
- "rm7_fpmpy+(rm7_fpmpy_iter*2)")
+ (and (eq_attr "cpu" "r7000")
+ (and (eq_attr "type" "fmul,fmadd")
+ (eq_attr "mode" "DF")))
+ "rm7_fpmpy+(rm7_fpmpy_iter*2)")
;; Force single-dispatch for unknown or multi.
-(define_insn_reservation "rm7_unknown" 1 (and (eq_attr "cpu" "r7000")
- (eq_attr "type" "unknown,multi"))
- "rm7_single_dispatch")
+(define_insn_reservation "rm7_unknown" 1
+ (and (eq_attr "cpu" "r7000")
+ (eq_attr "type" "unknown,multi"))
+ "rm7_single_dispatch")
;;
-(define_insn_reservation "ir_sr70_unknown"
- 1
- (and (eq_attr "cpu" "sr71000")
- (eq_attr "type" "unknown"))
- "serial_dispatch")
+(define_insn_reservation "ir_sr70_unknown" 1
+ (and (eq_attr "cpu" "sr71000")
+ (eq_attr "type" "unknown"))
+ "serial_dispatch")
;; Assume prediction fails.
-(define_insn_reservation "ir_sr70_branch"
- 6
- (and (eq_attr "cpu" "sr71000")
- (eq_attr "type" "branch,jump,call"))
- "ri_branch")
+(define_insn_reservation "ir_sr70_branch" 6
+ (and (eq_attr "cpu" "sr71000")
+ (eq_attr "type" "branch,jump,call"))
+ "ri_branch")
-(define_insn_reservation "ir_sr70_load"
- 2
- (and (eq_attr "cpu" "sr71000")
- (eq_attr "type" "load"))
- "ri_mem")
+(define_insn_reservation "ir_sr70_load" 2
+ (and (eq_attr "cpu" "sr71000")
+ (eq_attr "type" "load"))
+ "ri_mem")
-(define_insn_reservation "ir_sr70_store"
- 1
- (and (eq_attr "cpu" "sr71000")
- (eq_attr "type" "store"))
- "ri_mem")
+(define_insn_reservation "ir_sr70_store" 1
+ (and (eq_attr "cpu" "sr71000")
+ (eq_attr "type" "store"))
+ "ri_mem")
;;
;; float loads/stores flow through both cpu and cp1...
;;
-(define_insn_reservation "ir_sr70_fload"
- 9
- (and (eq_attr "cpu" "sr71000")
- (eq_attr "type" "fpload,fpidxload"))
- "(cpu_iss+cp1_iss),(ri_mem+rf_ldmem)")
+(define_insn_reservation "ir_sr70_fload" 9
+ (and (eq_attr "cpu" "sr71000")
+ (eq_attr "type" "fpload,fpidxload"))
+ "(cpu_iss+cp1_iss),(ri_mem+rf_ldmem)")
-(define_insn_reservation "ir_sr70_fstore"
- 1
- (and (eq_attr "cpu" "sr71000")
- (eq_attr "type" "fpstore,fpidxstore"))
- "(cpu_iss+cp1_iss),(fpu_mov+ri_mem)")
+(define_insn_reservation "ir_sr70_fstore" 1
+ (and (eq_attr "cpu" "sr71000")
+ (eq_attr "type" "fpstore,fpidxstore"))
+ "(cpu_iss+cp1_iss),(fpu_mov+ri_mem)")
;; This reservation is for conditional move based on integer
;; or floating point CC.
-(define_insn_reservation "ir_sr70_condmove"
- 4
- (and (eq_attr "cpu" "sr71000")
- (eq_attr "type" "condmove"))
- "ri_insns")
+(define_insn_reservation "ir_sr70_condmove" 4
+ (and (eq_attr "cpu" "sr71000")
+ (eq_attr "type" "condmove"))
+ "ri_insns")
;; Try to discriminate move-from-cp1 versus move-to-cp1 as latencies
;; are different. Like float load/store, these insns use multiple
;; resources simultaneously
-(define_insn_reservation "ir_sr70_xfer_from"
- 6
- (and (eq_attr "cpu" "sr71000")
- (and (eq_attr "type" "xfer")
- (eq_attr "mode" "!SF,DF,FPSW")))
- "(cpu_iss+cp1_iss),(fpu_mov+ri_mem)")
-
-(define_insn_reservation "ir_sr70_xfer_to"
- 9
- (and (eq_attr "cpu" "sr71000")
- (and (eq_attr "type" "xfer")
- (eq_attr "mode" "SF,DF")))
- "(cpu_iss+cp1_iss),(ri_mem+rf_ldmem)")
-
-(define_insn_reservation "ir_sr70_hilo"
- 1
- (and (eq_attr "cpu" "sr71000")
- (eq_attr "type" "mthilo,mfhilo"))
- "ri_insns")
-
-(define_insn_reservation "ir_sr70_arith"
- 1
- (and (eq_attr "cpu" "sr71000")
- (eq_attr "type" "arith,shift,slt,clz,const,trap"))
- "ri_insns")
+(define_insn_reservation "ir_sr70_xfer_from" 6
+ (and (eq_attr "cpu" "sr71000")
+ (and (eq_attr "type" "xfer")
+ (eq_attr "mode" "!SF,DF,FPSW")))
+ "(cpu_iss+cp1_iss),(fpu_mov+ri_mem)")
+
+(define_insn_reservation "ir_sr70_xfer_to" 9
+ (and (eq_attr "cpu" "sr71000")
+ (and (eq_attr "type" "xfer")
+ (eq_attr "mode" "SF,DF")))
+ "(cpu_iss+cp1_iss),(ri_mem+rf_ldmem)")
+
+(define_insn_reservation "ir_sr70_hilo" 1
+ (and (eq_attr "cpu" "sr71000")
+ (eq_attr "type" "mthilo,mfhilo"))
+ "ri_insns")
+
+(define_insn_reservation "ir_sr70_arith" 1
+ (and (eq_attr "cpu" "sr71000")
+ (eq_attr "type" "arith,shift,slt,clz,const,trap"))
+ "ri_insns")
;; emulate repeat (dispatch stall) by spending extra cycle(s) in
;; in iter unit
-(define_insn_reservation "ir_sr70_imul_si"
- 4
- (and (eq_attr "cpu" "sr71000")
- (and (eq_attr "type" "imul,imul3,imadd")
- (eq_attr "mode" "SI")))
- "ri_alux,ipu_alux,ipu_macc_iter")
-
-(define_insn_reservation "ir_sr70_imul_di"
- 6
- (and (eq_attr "cpu" "sr71000")
- (and (eq_attr "type" "imul,imul3,imadd")
- (eq_attr "mode" "DI")))
- "ri_alux,ipu_alux,(ipu_macc_iter*3)")
+(define_insn_reservation "ir_sr70_imul_si" 4
+ (and (eq_attr "cpu" "sr71000")
+ (and (eq_attr "type" "imul,imul3,imadd")
+ (eq_attr "mode" "SI")))
+ "ri_alux,ipu_alux,ipu_macc_iter")
+
+(define_insn_reservation "ir_sr70_imul_di" 6
+ (and (eq_attr "cpu" "sr71000")
+ (and (eq_attr "type" "imul,imul3,imadd")
+ (eq_attr "mode" "DI")))
+ "ri_alux,ipu_alux,(ipu_macc_iter*3)")
;; Divide algorithm is early out with best latency of 7 pcycles.
;; Use worst case for scheduling purposes.
-(define_insn_reservation "ir_sr70_idiv_si"
- 41
- (and (eq_attr "cpu" "sr71000")
- (and (eq_attr "type" "idiv")
- (eq_attr "mode" "SI")))
- "ri_alux,ipu_alux,(ipu_macc_iter*38)")
-
-(define_insn_reservation "ir_sr70_idiv_di"
- 73
- (and (eq_attr "cpu" "sr71000")
- (and (eq_attr "type" "idiv")
- (eq_attr "mode" "DI")))
- "ri_alux,ipu_alux,(ipu_macc_iter*70)")
+(define_insn_reservation "ir_sr70_idiv_si" 41
+ (and (eq_attr "cpu" "sr71000")
+ (and (eq_attr "type" "idiv")
+ (eq_attr "mode" "SI")))
+ "ri_alux,ipu_alux,(ipu_macc_iter*38)")
+
+(define_insn_reservation "ir_sr70_idiv_di" 73
+ (and (eq_attr "cpu" "sr71000")
+ (and (eq_attr "type" "idiv")
+ (eq_attr "mode" "DI")))
+ "ri_alux,ipu_alux,(ipu_macc_iter*70)")
;; extra reservations of fpu_fpu are for repeat latency
-(define_insn_reservation "ir_sr70_fadd_sf"
- 8
- (and (eq_attr "cpu" "sr71000")
- (and (eq_attr "type" "fadd")
- (eq_attr "mode" "SF")))
- "rf_insn,fpu_fpu")
-
-(define_insn_reservation "ir_sr70_fadd_df"
- 10
- (and (eq_attr "cpu" "sr71000")
- (and (eq_attr "type" "fadd")
- (eq_attr "mode" "DF")))
- "rf_insn,fpu_fpu")
+(define_insn_reservation "ir_sr70_fadd_sf" 8
+ (and (eq_attr "cpu" "sr71000")
+ (and (eq_attr "type" "fadd")
+ (eq_attr "mode" "SF")))
+ "rf_insn,fpu_fpu")
+
+(define_insn_reservation "ir_sr70_fadd_df" 10
+ (and (eq_attr "cpu" "sr71000")
+ (and (eq_attr "type" "fadd")
+ (eq_attr "mode" "DF")))
+ "rf_insn,fpu_fpu")
;; Latencies for MADD,MSUB, NMADD, NMSUB assume the Multiply is fused
;; with the sub or add.
-(define_insn_reservation "ir_sr70_fmul_sf"
- 8
- (and (eq_attr "cpu" "sr71000")
- (and (eq_attr "type" "fmul,fmadd")
- (eq_attr "mode" "SF")))
- "rf_insn,fpu_fpu")
+(define_insn_reservation "ir_sr70_fmul_sf" 8
+ (and (eq_attr "cpu" "sr71000")
+ (and (eq_attr "type" "fmul,fmadd")
+ (eq_attr "mode" "SF")))
+ "rf_insn,fpu_fpu")
;; tie up the fpu unit to emulate the balance for the "repeat
;; rate" of 8 (2 are spent in the iss unit)
-(define_insn_reservation "ir_sr70_fmul_df"
- 16
- (and (eq_attr "cpu" "sr71000")
- (and (eq_attr "type" "fmul,fmadd")
- (eq_attr "mode" "DF")))
- "rf_insn,fpu_fpu*6")
+(define_insn_reservation "ir_sr70_fmul_df" 16
+ (and (eq_attr "cpu" "sr71000")
+ (and (eq_attr "type" "fmul,fmadd")
+ (eq_attr "mode" "DF")))
+ "rf_insn,fpu_fpu*6")
;; RECIP insn uses same type attr as div, and for SR3, has same
;; 28 -- only way to fix this is to introduce new insn attrs.
;; cycles spent in iter unit are designed to satisfy balance
;; of "repeat" latency after insn uses up rf_multi1 reservation
-(define_insn_reservation "ir_sr70_fdiv_sf"
- 60
- (and (eq_attr "cpu" "sr71000")
- (and (eq_attr "type" "fdiv,frdiv")
- (eq_attr "mode" "SF")))
- "rf_multi1+(fpu_iter*51)")
-
-(define_insn_reservation "ir_sr70_fdiv_df"
- 120
- (and (eq_attr "cpu" "sr71000")
- (and (eq_attr "type" "fdiv,frdiv")
- (eq_attr "mode" "DF")))
- "rf_multi1+(fpu_iter*109)")
-
-(define_insn_reservation "ir_sr70_fabs"
- 4
- (and (eq_attr "cpu" "sr71000")
- (eq_attr "type" "fabs,fneg,fmove"))
- "rf_insn,fpu_fpu")
-
-(define_insn_reservation "ir_sr70_fcmp"
- 10
- (and (eq_attr "cpu" "sr71000")
- (eq_attr "type" "fcmp"))
- "rf_insn,fpu_fpu")
+(define_insn_reservation "ir_sr70_fdiv_sf" 60
+ (and (eq_attr "cpu" "sr71000")
+ (and (eq_attr "type" "fdiv,frdiv")
+ (eq_attr "mode" "SF")))
+ "rf_multi1+(fpu_iter*51)")
+
+(define_insn_reservation "ir_sr70_fdiv_df" 120
+ (and (eq_attr "cpu" "sr71000")
+ (and (eq_attr "type" "fdiv,frdiv")
+ (eq_attr "mode" "DF")))
+ "rf_multi1+(fpu_iter*109)")
+
+(define_insn_reservation "ir_sr70_fabs" 4
+ (and (eq_attr "cpu" "sr71000")
+ (eq_attr "type" "fabs,fneg,fmove"))
+ "rf_insn,fpu_fpu")
+
+(define_insn_reservation "ir_sr70_fcmp" 10
+ (and (eq_attr "cpu" "sr71000")
+ (eq_attr "type" "fcmp"))
+ "rf_insn,fpu_fpu")
;; "fcvt" type attribute covers a number of diff insns, most have the same
;; latency descriptions, a few vary. We use the
;; most common timing (which is also worst case).
-(define_insn_reservation "ir_sr70_fcvt"
- 12
- (and (eq_attr "cpu" "sr71000")
- (eq_attr "type" "fcvt"))
- "rf_insn,fpu_fpu*4")
-
-(define_insn_reservation "ir_sr70_fsqrt_sf"
- 62
- (and (eq_attr "cpu" "sr71000")
- (and (eq_attr "type" "fsqrt")
- (eq_attr "mode" "SF")))
- "rf_multi1+(fpu_iter*53)")
-
-(define_insn_reservation "ir_sr70_fsqrt_df"
- 122
- (and (eq_attr "cpu" "sr71000")
- (and (eq_attr "type" "fsqrt")
- (eq_attr "mode" "DF")))
- "rf_multi1+(fpu_iter*111)")
-
-(define_insn_reservation "ir_sr70_frsqrt_sf"
- 48
- (and (eq_attr "cpu" "sr71000")
- (and (eq_attr "type" "frsqrt")
- (eq_attr "mode" "SF")))
- "rf_multi1+(fpu_iter*39)")
-
-(define_insn_reservation "ir_sr70_frsqrt_df"
- 240
- (and (eq_attr "cpu" "sr71000")
- (and (eq_attr "type" "frsqrt")
- (eq_attr "mode" "DF")))
- "rf_multi1+(fpu_iter*229)")
-
-(define_insn_reservation "ir_sr70_multi"
- 1
- (and (eq_attr "cpu" "sr71000")
- (eq_attr "type" "multi"))
- "serial_dispatch")
-
-(define_insn_reservation "ir_sr70_nop"
- 1
- (and (eq_attr "cpu" "sr71000")
- (eq_attr "type" "nop"))
- "ri_insns")
+(define_insn_reservation "ir_sr70_fcvt" 12
+ (and (eq_attr "cpu" "sr71000")
+ (eq_attr "type" "fcvt"))
+ "rf_insn,fpu_fpu*4")
+
+(define_insn_reservation "ir_sr70_fsqrt_sf" 62
+ (and (eq_attr "cpu" "sr71000")
+ (and (eq_attr "type" "fsqrt")
+ (eq_attr "mode" "SF")))
+ "rf_multi1+(fpu_iter*53)")
+
+(define_insn_reservation "ir_sr70_fsqrt_df" 122
+ (and (eq_attr "cpu" "sr71000")
+ (and (eq_attr "type" "fsqrt")
+ (eq_attr "mode" "DF")))
+ "rf_multi1+(fpu_iter*111)")
+
+(define_insn_reservation "ir_sr70_frsqrt_sf" 48
+ (and (eq_attr "cpu" "sr71000")
+ (and (eq_attr "type" "frsqrt")
+ (eq_attr "mode" "SF")))
+ "rf_multi1+(fpu_iter*39)")
+
+(define_insn_reservation "ir_sr70_frsqrt_df" 240
+ (and (eq_attr "cpu" "sr71000")
+ (and (eq_attr "type" "frsqrt")
+ (eq_attr "mode" "DF")))
+ "rf_multi1+(fpu_iter*229)")
+
+(define_insn_reservation "ir_sr70_multi" 1
+ (and (eq_attr "cpu" "sr71000")
+ (eq_attr "type" "multi"))
+ "serial_dispatch")
+
+(define_insn_reservation "ir_sr70_nop" 1
+ (and (eq_attr "cpu" "sr71000")
+ (eq_attr "type" "nop"))
+ "ri_insns")
projects / platform / upstream / linaro-gcc.git / commitdiff