[PATCH] x86_64: miscellaneous cleanup

- adjust limits of GDT/IDT pseudo-descriptors (some were off by one)
- move empty_zero_page into .bss.page_aligned
- move cpu_gdt_table into .data.page_aligned
- move idt_table into .bss
- align inital_code and init_rsp
- eliminate pointless (re-)declaration of idt_table in traps.c

Signed-off-by: Jan Beulich <jbeulich@novell.com>
Signed-off-by: Andi Kleen <ak@suse.de>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>

diff --git a/arch/x86_64/kernel/head.S b/arch/x86_64/kernel/head.S
index 02fc7fa..0cddcc0 100644 (file)
--- a/arch/x86_64/kernel/head.S
+++ b/arch/x86_64/kernel/head.S
@@ -192,7 +192,8 @@ startup_64:
        movq    initial_code(%rip),%rax
        jmp     *%rax
 
-       /* SMP bootup changes these two */      
+       /* SMP bootup changes these two */
+       .align  8
        .globl  initial_code
 initial_code:
        .quad   x86_64_start_kernel
@@ -237,7 +238,7 @@ ENTRY(no_long_mode)
 .org 0xf00
        .globl pGDT32
 pGDT32:
-       .word   gdt_end-cpu_gdt_table
+       .word   gdt_end-cpu_gdt_table-1
        .long   cpu_gdt_table-__START_KERNEL_map
 
 .org 0xf10     
@@ -293,8 +294,6 @@ NEXT_PAGE(level2_kernel_pgt)
        /* Module mapping starts here */
        .fill   492,8,0
 
-NEXT_PAGE(empty_zero_page)
-
 NEXT_PAGE(level3_physmem_pgt)
        .quad   phys_level2_kernel_pgt | 0x007  /* so that __va works even before pagetable_init */
        .fill   511,8,0
@@ -337,7 +336,7 @@ ENTRY(boot_level4_pgt)
        .align 16
        .globl cpu_gdt_descr
 cpu_gdt_descr:
-       .word   gdt_end-cpu_gdt_table
+       .word   gdt_end-cpu_gdt_table-1
 gdt:
        .quad   cpu_gdt_table
 #ifdef CONFIG_SMP
@@ -352,7 +351,8 @@ gdt:
  * Also sysret mandates a special GDT layout 
  */
                                
-.align PAGE_SIZE
+       .section .data.page_aligned, "aw"
+       .align PAGE_SIZE
 
 /* The TLS descriptors are currently at a different place compared to i386.
    Hopefully nobody expects them at a fixed place (Wine?) */
@@ -378,9 +378,12 @@ gdt_end:
        /* zero the remaining page */
        .fill PAGE_SIZE / 8 - GDT_ENTRIES,8,0
 
-ENTRY(idt_table)       
-       .rept   256
-       .quad   0
-       .quad   0
-       .endr
+       .section .bss, "aw", @nobits
+       .align L1_CACHE_BYTES
+ENTRY(idt_table)
+       .skip 256 * 16
 
+       .section .bss.page_aligned, "aw", @nobits
+       .align PAGE_SIZE
+ENTRY(empty_zero_page)
+       .skip PAGE_SIZE

diff --git a/arch/x86_64/kernel/setup64.c b/arch/x86_64/kernel/setup64.c
index 0445878..356b462 100644 (file)
--- a/arch/x86_64/kernel/setup64.c
+++ b/arch/x86_64/kernel/setup64.c
@@ -33,7 +33,7 @@ cpumask_t cpu_initialized __cpuinitdata = CPU_MASK_NONE;
 struct x8664_pda *_cpu_pda[NR_CPUS] __read_mostly;
 struct x8664_pda boot_cpu_pda[NR_CPUS] __cacheline_aligned;
 
-struct desc_ptr idt_descr = { 256 * 16, (unsigned long) idt_table }; 
+struct desc_ptr idt_descr = { 256 * 16 - 1, (unsigned long) idt_table };
 
 char boot_cpu_stack[IRQSTACKSIZE] __attribute__((section(".bss.page_aligned")));
 

diff --git a/arch/x86_64/kernel/traps.c b/arch/x86_64/kernel/traps.c
index 05dbbf4..7b14830 100644 (file)
--- a/arch/x86_64/kernel/traps.c
+++ b/arch/x86_64/kernel/traps.c
@@ -47,8 +47,6 @@
 #include <asm/proto.h>
 #include <asm/nmi.h>
 
-extern struct gate_struct idt_table[256]; 
-
 asmlinkage void divide_error(void);
 asmlinkage void debug(void);
 asmlinkage void nmi(void);