drm/i915: split out intel_display_reg_defs.h

Split out the display register helper macros to a separate file. For
now, include it from i915_reg.h, but note that there are already files
that don't need i915_reg.h, such as intel_audio.c.

Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/3af47193ff5219b6d2cfe353b752ec4bb44de4f1.1668008071.git.jani.nikula@intel.com

diff --git a/drivers/gpu/drm/i915/display/icl_dsi_regs.h b/drivers/gpu/drm/i915/display/icl_dsi_regs.h
index f78f28b..d4845ac 100644 (file)
--- a/drivers/gpu/drm/i915/display/icl_dsi_regs.h
+++ b/drivers/gpu/drm/i915/display/icl_dsi_regs.h
@@ -6,7 +6,7 @@
 #ifndef __ICL_DSI_REGS_H__
 #define __ICL_DSI_REGS_H__
 
-#include "i915_reg_defs.h"
+#include "intel_display_reg_defs.h"
 
 /* Gen11 DSI */
 #define _MMIO_DSI(tc, dsi0, dsi1)      _MMIO_TRANS((tc) - TRANSCODER_DSI_0, \

diff --git a/drivers/gpu/drm/i915/display/intel_audio_regs.h b/drivers/gpu/drm/i915/display/intel_audio_regs.h
index 4f432c2..616e7b1 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_audio_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_audio_regs.h
@@ -6,7 +6,7 @@
 #ifndef __INTEL_AUDIO_REGS_H__
 #define __INTEL_AUDIO_REGS_H__
 
-#include "i915_reg_defs.h"
+#include "intel_display_reg_defs.h"
 
 #define G4X_AUD_CNTL_ST                        _MMIO(0x620B4)
 #define   G4X_ELD_VALID                        REG_BIT(14)

diff --git a/drivers/gpu/drm/i915/display/intel_backlight_regs.h b/drivers/gpu/drm/i915/display/intel_backlight_regs.h
index 50c1210..344eb80 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_backlight_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_backlight_regs.h
@@ -6,7 +6,7 @@
 #ifndef __INTEL_BACKLIGHT_REGS_H__
 #define __INTEL_BACKLIGHT_REGS_H__
 
-#include "i915_reg_defs.h"
+#include "intel_display_reg_defs.h"
 
 #define _VLV_BLC_PWM_CTL2_A (DISPLAY_MMIO_BASE(dev_priv) + 0x61250)
 #define _VLV_BLC_PWM_CTL2_B (DISPLAY_MMIO_BASE(dev_priv) + 0x61350)

diff --git a/drivers/gpu/drm/i915/display/intel_display_reg_defs.h b/drivers/gpu/drm/i915/display/intel_display_reg_defs.h
new file mode 100644 (file)
index 0000000..0260541
--- /dev/null
+++ b/drivers/gpu/drm/i915/display/intel_display_reg_defs.h
@@ -0,0 +1,53 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2022 Intel Corporation
+ */
+
+#ifndef __INTEL_DISPLAY_REG_DEFS_H__
+#define __INTEL_DISPLAY_REG_DEFS_H__
+
+#include "i915_reg_defs.h"
+
+#define DISPLAY_MMIO_BASE(dev_priv)    (INTEL_INFO(dev_priv)->display.mmio_offset)
+
+#define VLV_DISPLAY_BASE               0x180000
+
+/*
+ * Named helper wrappers around _PICK_EVEN() and _PICK().
+ */
+#define _PIPE(pipe, a, b)              _PICK_EVEN(pipe, a, b)
+#define _PLANE(plane, a, b)            _PICK_EVEN(plane, a, b)
+#define _TRANS(tran, a, b)             _PICK_EVEN(tran, a, b)
+#define _PORT(port, a, b)              _PICK_EVEN(port, a, b)
+#define _PLL(pll, a, b)                        _PICK_EVEN(pll, a, b)
+#define _PHY(phy, a, b)                        _PICK_EVEN(phy, a, b)
+
+#define _MMIO_PIPE(pipe, a, b)         _MMIO(_PIPE(pipe, a, b))
+#define _MMIO_PLANE(plane, a, b)       _MMIO(_PLANE(plane, a, b))
+#define _MMIO_TRANS(tran, a, b)                _MMIO(_TRANS(tran, a, b))
+#define _MMIO_PORT(port, a, b)         _MMIO(_PORT(port, a, b))
+#define _MMIO_PLL(pll, a, b)           _MMIO(_PLL(pll, a, b))
+#define _MMIO_PHY(phy, a, b)           _MMIO(_PHY(phy, a, b))
+
+#define _PHY3(phy, ...)                        _PICK(phy, __VA_ARGS__)
+
+#define _MMIO_PIPE3(pipe, a, b, c)     _MMIO(_PICK(pipe, a, b, c))
+#define _MMIO_PORT3(pipe, a, b, c)     _MMIO(_PICK(pipe, a, b, c))
+#define _MMIO_PHY3(phy, a, b, c)       _MMIO(_PHY3(phy, a, b, c))
+#define _MMIO_PLL3(pll, ...)           _MMIO(_PICK(pll, __VA_ARGS__))
+
+/*
+ * Device info offset array based helpers for groups of registers with unevenly
+ * spaced base offsets.
+ */
+#define _MMIO_PIPE2(pipe, reg)         _MMIO(INTEL_INFO(dev_priv)->display.pipe_offsets[(pipe)] - \
+                                             INTEL_INFO(dev_priv)->display.pipe_offsets[PIPE_A] + \
+                                             DISPLAY_MMIO_BASE(dev_priv) + (reg))
+#define _MMIO_TRANS2(tran, reg)                _MMIO(INTEL_INFO(dev_priv)->display.trans_offsets[(tran)] - \
+                                             INTEL_INFO(dev_priv)->display.trans_offsets[TRANSCODER_A] + \
+                                             DISPLAY_MMIO_BASE(dev_priv) + (reg))
+#define _MMIO_CURSOR2(pipe, reg)       _MMIO(INTEL_INFO(dev_priv)->display.cursor_offsets[(pipe)] - \
+                                             INTEL_INFO(dev_priv)->display.cursor_offsets[PIPE_A] + \
+                                             DISPLAY_MMIO_BASE(dev_priv) + (reg))
+
+#endif /* __INTEL_DISPLAY_REG_DEFS_H__ */

diff --git a/drivers/gpu/drm/i915/display/intel_hdcp_regs.h b/drivers/gpu/drm/i915/display/intel_hdcp_regs.h
index 2a3733e..8023c85 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_hdcp_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_hdcp_regs.h
@@ -6,7 +6,7 @@
 #ifndef __INTEL_HDCP_REGS_H__
 #define __INTEL_HDCP_REGS_H__
 
-#include "i915_reg_defs.h"
+#include "intel_display_reg_defs.h"
 
 /* HDCP Key Registers */
 #define HDCP_KEY_CONF                  _MMIO(0x66c00)

diff --git a/drivers/gpu/drm/i915/display/intel_mg_phy_regs.h b/drivers/gpu/drm/i915/display/intel_mg_phy_regs.h
index 07978f8..0e8248b 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_mg_phy_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_mg_phy_regs.h
@@ -6,7 +6,7 @@
 #ifndef __INTEL_MG_PHY_REGS__
 #define __INTEL_MG_PHY_REGS__
 
-#include "i915_reg_defs.h"
+#include "intel_display_reg_defs.h"
 
 #define MG_PHY_PORT_LN(ln, tc_port, ln0p1, ln0p2, ln1p1) \
        _MMIO(_PORT(tc_port, ln0p1, ln0p2) + (ln) * ((ln1p1) - (ln0p1)))

diff --git a/drivers/gpu/drm/i915/display/intel_snps_phy_regs.h b/drivers/gpu/drm/i915/display/intel_snps_phy_regs.h
index 0543465..a04d692 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_snps_phy_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_snps_phy_regs.h
@@ -6,7 +6,7 @@
 #ifndef __INTEL_SNPS_PHY_REGS__
 #define __INTEL_SNPS_PHY_REGS__
 
-#include "i915_reg_defs.h"
+#include "intel_display_reg_defs.h"
 
 #define _SNPS_PHY_A_BASE                       0x168000
 #define _SNPS_PHY_B_BASE                       0x169000

diff --git a/drivers/gpu/drm/i915/display/vlv_dsi_regs.h b/drivers/gpu/drm/i915/display/vlv_dsi_regs.h
index e065b8f..abbe427 100644 (file)
--- a/drivers/gpu/drm/i915/display/vlv_dsi_regs.h
+++ b/drivers/gpu/drm/i915/display/vlv_dsi_regs.h
@@ -6,7 +6,7 @@
 #ifndef __VLV_DSI_REGS_H__
 #define __VLV_DSI_REGS_H__
 
-#include "i915_reg_defs.h"
+#include "intel_display_reg_defs.h"
 
 #define VLV_MIPI_BASE                  VLV_DISPLAY_BASE
 #define BXT_MIPI_BASE                  0x60000

diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
index 94a0606..fb0c61b 100644 (file)
--- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
@@ -7,6 +7,7 @@
 #define __INTEL_GT_REGS__
 
 #include "i915_reg_defs.h"
+#include "display/intel_display_reg_defs.h"    /* VLV_DISPLAY_BASE */
 
 /* RPM unit config (Gen8+) */
 #define RPM_CONFIG0                            _MMIO(0xd00)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index f0e6da4..93f3b7e 100644 (file)
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -26,6 +26,7 @@
 #define _I915_REG_H_
 
 #include "i915_reg_defs.h"
+#include "display/intel_display_reg_defs.h"
 
 /**
  * DOC: The i915 register macro definition style guide
@@ -115,47 +116,6 @@
  *  #define GEN8_BAR                    _MMIO(0xb888)
  */
 
-#define DISPLAY_MMIO_BASE(dev_priv)    (INTEL_INFO(dev_priv)->display.mmio_offset)
-
-/*
- * Named helper wrappers around _PICK_EVEN() and _PICK().
- */
-#define _PIPE(pipe, a, b)              _PICK_EVEN(pipe, a, b)
-#define _PLANE(plane, a, b)            _PICK_EVEN(plane, a, b)
-#define _TRANS(tran, a, b)             _PICK_EVEN(tran, a, b)
-#define _PORT(port, a, b)              _PICK_EVEN(port, a, b)
-#define _PLL(pll, a, b)                        _PICK_EVEN(pll, a, b)
-#define _PHY(phy, a, b)                        _PICK_EVEN(phy, a, b)
-
-#define _MMIO_PIPE(pipe, a, b)         _MMIO(_PIPE(pipe, a, b))
-#define _MMIO_PLANE(plane, a, b)       _MMIO(_PLANE(plane, a, b))
-#define _MMIO_TRANS(tran, a, b)                _MMIO(_TRANS(tran, a, b))
-#define _MMIO_PORT(port, a, b)         _MMIO(_PORT(port, a, b))
-#define _MMIO_PLL(pll, a, b)           _MMIO(_PLL(pll, a, b))
-#define _MMIO_PHY(phy, a, b)           _MMIO(_PHY(phy, a, b))
-
-#define _PHY3(phy, ...)                        _PICK(phy, __VA_ARGS__)
-
-#define _MMIO_PIPE3(pipe, a, b, c)     _MMIO(_PICK(pipe, a, b, c))
-#define _MMIO_PORT3(pipe, a, b, c)     _MMIO(_PICK(pipe, a, b, c))
-#define _MMIO_PHY3(phy, a, b, c)       _MMIO(_PHY3(phy, a, b, c))
-#define _MMIO_PLL3(pll, ...)           _MMIO(_PICK(pll, __VA_ARGS__))
-
-
-/*
- * Device info offset array based helpers for groups of registers with unevenly
- * spaced base offsets.
- */
-#define _MMIO_PIPE2(pipe, reg)         _MMIO(INTEL_INFO(dev_priv)->display.pipe_offsets[(pipe)] - \
-                                             INTEL_INFO(dev_priv)->display.pipe_offsets[PIPE_A] + \
-                                             DISPLAY_MMIO_BASE(dev_priv) + (reg))
-#define _MMIO_TRANS2(tran, reg)                _MMIO(INTEL_INFO(dev_priv)->display.trans_offsets[(tran)] - \
-                                             INTEL_INFO(dev_priv)->display.trans_offsets[TRANSCODER_A] + \
-                                             DISPLAY_MMIO_BASE(dev_priv) + (reg))
-#define _MMIO_CURSOR2(pipe, reg)       _MMIO(INTEL_INFO(dev_priv)->display.cursor_offsets[(pipe)] - \
-                                             INTEL_INFO(dev_priv)->display.cursor_offsets[PIPE_A] + \
-                                             DISPLAY_MMIO_BASE(dev_priv) + (reg))
-
 #define GU_CNTL                                _MMIO(0x101010)
 #define   LMEM_INIT                    REG_BIT(7)
 

diff --git a/drivers/gpu/drm/i915/i915_reg_defs.h b/drivers/gpu/drm/i915/i915_reg_defs.h
index 344e500..1564f2c 100644 (file)
--- a/drivers/gpu/drm/i915/i915_reg_defs.h
+++ b/drivers/gpu/drm/i915/i915_reg_defs.h
@@ -149,6 +149,4 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
        return !i915_mmio_reg_equal(reg, INVALID_MMIO_REG);
 }
 
-#define VLV_DISPLAY_BASE               0x180000
-
 #endif /* __I915_REG_DEFS__ */