* Note: 0 <= counter_index < SBI_PMU_HW_CTR_MAX
*/
void (*hw_counter_disable_irq)(uint32_t counter_index);
+
+ /**
+ * Custom function returning the machine-specific irq-bit.
+ */
+ int (*hw_counter_irq_bit)(void);
};
/** Get the PMU platform device */
/** Reset PMU during hart exit */
void sbi_pmu_exit(struct sbi_scratch *scratch);
+/** Return the pmu irq bit depending on extension existence */
+int sbi_pmu_irq_bit(void);
+
/**
* Add the hardware event to counter mapping information. This should be called
* from the platform code to update the mapping table.
#include <sbi/sbi_hart.h>
#include <sbi/sbi_math.h>
#include <sbi/sbi_platform.h>
+#include <sbi/sbi_pmu.h>
#include <sbi/sbi_string.h>
#include <sbi/sbi_trap.h>
/* Send M-mode interrupts and most exceptions to S-mode */
interrupts = MIP_SSIP | MIP_STIP | MIP_SEIP;
- if (sbi_hart_has_extension(scratch, SBI_HART_EXT_SSCOFPMF))
- interrupts |= MIP_LCOFIP;
+ interrupts |= sbi_pmu_irq_bit();
exceptions = (1U << CAUSE_MISALIGNED_FETCH) | (1U << CAUSE_BREAKPOINT) |
(1U << CAUSE_USER_ECALL);
return 0;
}
+int sbi_pmu_irq_bit(void)
+{
+ struct sbi_scratch *scratch = sbi_scratch_thishart_ptr();
+
+ if (sbi_hart_has_extension(scratch, SBI_HART_EXT_SSCOFPMF))
+ return MIP_LCOFIP;
+ if (pmu_dev && pmu_dev->hw_counter_irq_bit)
+ return pmu_dev->hw_counter_irq_bit();
+
+ return 0;
+}
+
static int pmu_ctr_start_fw(uint32_t cidx, uint32_t event_code,
uint64_t ival, bool ival_update)
{