drm/amdgpu: simplify the sdma 4_x MGCG/MGLS logic.

SDMA 4_x asics share the same MGCG/MGLS setting.

Signed-off-by: Feifei Xu <Feifei.Xu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Lijo Lazar <lijo.lazar@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
index 00d3773..fdc0c81 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
@@ -2222,21 +2222,10 @@ static int sdma_v4_0_set_clockgating_state(void *handle,
        if (amdgpu_sriov_vf(adev))
                return 0;
 
-       switch (adev->asic_type) {
-       case CHIP_VEGA10:
-       case CHIP_VEGA12:
-       case CHIP_VEGA20:
-       case CHIP_RAVEN:
-       case CHIP_ARCTURUS:
-       case CHIP_RENOIR:
-               sdma_v4_0_update_medium_grain_clock_gating(adev,
-                               state == AMD_CG_STATE_GATE);
-               sdma_v4_0_update_medium_grain_light_sleep(adev,
-                               state == AMD_CG_STATE_GATE);
-               break;
-       default:
-               break;
-       }
+       sdma_v4_0_update_medium_grain_clock_gating(adev,
+                       state == AMD_CG_STATE_GATE);
+       sdma_v4_0_update_medium_grain_light_sleep(adev,
+                       state == AMD_CG_STATE_GATE);
        return 0;
 }