chip->wr_ch_cnt = vsec_data.wr_ch_cnt;
chip->rd_ch_cnt = vsec_data.rd_ch_cnt;
- chip->rg_region.vaddr = pcim_iomap_table(pdev)[vsec_data.rg.bar];
- if (!chip->rg_region.vaddr)
+ chip->reg_base = pcim_iomap_table(pdev)[vsec_data.rg.bar];
+ if (!chip->reg_base)
return -ENOMEM;
for (i = 0; i < chip->wr_ch_cnt; i++) {
pci_dbg(pdev, "Registers:\tBAR=%u, off=0x%.8lx, sz=0x%zx bytes, addr(v=%p)\n",
vsec_data.rg.bar, vsec_data.rg.off, vsec_data.rg.sz,
- chip->rg_region.vaddr);
+ chip->reg_base);
for (i = 0; i < chip->wr_ch_cnt; i++) {
static inline struct dw_edma_v0_regs __iomem *__dw_regs(struct dw_edma *dw)
{
- return dw->chip->rg_region.vaddr;
+ return dw->chip->reg_base;
}
#define SET_32(dw, name, value) \
* @id: instance ID
* @nr_irqs: total number of DMA IRQs
* @ops DMA channel to IRQ number mapping
+ * @reg_base DMA register base address
* @wr_ch_cnt DMA write channel number
* @rd_ch_cnt DMA read channel number
* @rg_region DMA register region
int nr_irqs;
const struct dw_edma_core_ops *ops;
- struct dw_edma_region rg_region;
+ void __iomem *reg_base;
u16 wr_ch_cnt;
u16 rd_ch_cnt;