return RegName.equals("esp") || RegName.equals("rsp");
}
- bool validateCpuSupports(StringRef Name) const override;
+ bool validateCpuSupports(StringRef FeatureStr) const override;
- bool validateCpuIs(StringRef Name) const override;
+ bool validateCpuIs(StringRef FeatureStr) const override;
bool validateCPUSpecificCPUDispatch(StringRef Name) const override;
std::string FeatureStr = OF.str();
FeatureStr[0] = std::toupper(FeatureStr[0]);
// Combine strings.
- FeatureStrs += FeatureStrs == "" ? "" : ", ";
+ FeatureStrs += FeatureStrs.empty() ? "" : ", ";
FeatureStrs += "'";
FeatureStrs += FeatureStr;
FeatureStrs += "'";
getSpecifierRange(startPos, posLen));
}
-void
-CheckFormatHandler::HandleInvalidPosition(const char *startPos, unsigned posLen,
- analyze_format_string::PositionContext p) {
- EmitFormatDiagnostic(S.PDiag(diag::warn_format_invalid_positional_specifier)
- << (unsigned) p,
- getLocationOfByte(startPos), /*IsStringLocation*/true,
- getSpecifierRange(startPos, posLen));
+void CheckFormatHandler::HandleInvalidPosition(
+ const char *startSpecifier, unsigned specifierLen,
+ analyze_format_string::PositionContext p) {
+ EmitFormatDiagnostic(
+ S.PDiag(diag::warn_format_invalid_positional_specifier) << (unsigned)p,
+ getLocationOfByte(startSpecifier), /*IsStringLocation*/ true,
+ getSpecifierRange(startSpecifier, specifierLen));
}
void CheckFormatHandler::HandleZeroPosition(const char *startPos,
void UncoveredArgHandler::Diagnose(Sema &S, bool IsFunctionCall,
const Expr *ArgExpr) {
- assert(hasUncoveredArg() && DiagnosticExprs.size() > 0 &&
+ assert(hasUncoveredArg() && !DiagnosticExprs.empty() &&
"Invalid state");
if (!ArgExpr)
namespace {
struct FindCaptureVisitor : EvaluatedExprVisitor<FindCaptureVisitor> {
- ASTContext &Context;
VarDecl *Variable;
Expr *Capturer = nullptr;
bool VarWillBeReased = false;
FindCaptureVisitor(ASTContext &Context, VarDecl *variable)
: EvaluatedExprVisitor<FindCaptureVisitor>(Context),
- Context(Context), Variable(variable) {}
+ Variable(variable) {}
void VisitDeclRefExpr(DeclRefExpr *ref) {
if (ref->getDecl() == Variable && !Capturer)
const X86MachineFunctionInfo *X86FI = nullptr;
const X86FrameLowering *X86FL = nullptr;
- bool runOnMachineFunction(MachineFunction &Fn) override;
+ bool runOnMachineFunction(MachineFunction &MF) override;
MachineFunctionProperties getRequiredProperties() const override {
return MachineFunctionProperties().set(
/// placed into separate block guarded by check for al register(for SystemV
/// abi).
void ExpandVastartSaveXmmRegs(
- MachineBasicBlock *MBB,
+ MachineBasicBlock *EntryBlk,
MachineBasicBlock::iterator VAStartPseudoInstr) const;
};
char X86ExpandPseudo::ID = 0;
unsigned MaxDepth, bool HasVariableMask, bool AllowVariableCrossLaneMask,
bool AllowVariablePerLaneMask, SelectionDAG &DAG,
const X86Subtarget &Subtarget) {
- assert(RootMask.size() > 0 &&
+ assert(!RootMask.empty() &&
(RootMask.size() > 1 || (RootMask[0] == 0 && SrcOpIndex == 0)) &&
"Illegal shuffle root mask");
MVT RootVT = Root.getSimpleValueType();
return SDValue();
// Try to lower nodes matching the or(or, setcc(eq, cmp 0)) pattern.
- while (ORNodes.size() > 0) {
+ while (!ORNodes.empty()) {
OR = ORNodes.pop_back_val();
LHS = OR->getOperand(0);
RHS = OR->getOperand(1);
resolveTargetShuffleInputsAndMask(SrcOps, SrcMask);
if (!UseSubVector && SrcOps.size() <= 2 &&
scaleShuffleElements(SrcMask, NumElts, ScaledMask)) {
- N0 = SrcOps.size() > 0 ? SrcOps[0] : SDValue();
+ N0 = !SrcOps.empty() ? SrcOps[0] : SDValue();
N1 = SrcOps.size() > 1 ? SrcOps[1] : SDValue();
ShuffleMask.assign(ScaledMask.begin(), ScaledMask.end());
}
SmallVector<Instruction *, 2> &Incomings);
void replacePhiDefWithLoad(Instruction *PHI, Value *StorePtr);
bool volatileTileData();
- void volatileTilePHI(PHINode *Inst);
+ void volatileTilePHI(PHINode *PHI);
void volatileTileNonPHI(Instruction *I);
};