ColdFire: Fix M5329EVB and M5373EVB nand issue

Fix compilation issue caused by a few mismatches.
Provide proper nand chip select enable/disable in
nand_hwcontrol() rather than in board_nand_init()
just enable once. Remove redundant local nand driver
functions - nand_read_byte(), nand_write_byte() and
nand_dev_ready() to use common nand driver.

Signed-off-by: TsiChung Liew <Tsi-Chung.Liew@freescale.com>

diff --git a/board/freescale/m5329evb/nand.c b/board/freescale/m5329evb/nand.c
index 82492f6..cf27dda 100644 (file)
--- a/board/freescale/m5329evb/nand.c
+++ b/board/freescale/m5329evb/nand.c
@@ -36,56 +36,42 @@ DECLARE_GLOBAL_DATA_PTR;
 #include <linux/mtd/mtd.h>
 
 #define SET_CLE                0x10
-#define CLR_CLE                ~SET_CLE
 #define SET_ALE                0x08
-#define CLR_ALE                ~SET_ALE
 
-static void nand_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
+static void nand_hwcontrol(struct mtd_info *mtdinfo, int cmd, unsigned int ctrl)
 {
        struct nand_chip *this = mtdinfo->priv;
-/*     volatile fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS; TODO: handle wp */
-       u32 nand_baseaddr = (u32) this->IO_ADDR_W;
+       volatile u16 *nCE = (u16 *) CONFIG_SYS_LATCH_ADDR;
 
        if (ctrl & NAND_CTRL_CHANGE) {
-               if ( ctrl & NAND_CLE )
-                       nand_baseaddr |= SET_CLE;
-               else
-                       nand_baseaddr &= CLR_CLE;
-               if ( ctrl & NAND_ALE )
-                       nand_baseaddr |= SET_ALE;
-               else
-                       nand_baseaddr &= CLR_ALE;
-       }
-       this->IO_ADDR_W = (void __iomem *)(nand_baseaddr);
+               ulong IO_ADDR_W = (ulong) this->IO_ADDR_W;
 
-       if (cmd != NAND_CMD_NONE)
-               writeb(cmd, this->IO_ADDR_W);
-}
+               IO_ADDR_W &= ~(SET_ALE | SET_CLE);
+               *nCE &= 0xFFFB;
 
-static void nand_write_byte(struct mtd_info *mtdinfo, u_char byte)
-{
-       struct nand_chip *this = mtdinfo->priv;
-       *((volatile u8 *)(this->IO_ADDR_W)) = byte;
-}
+               if (ctrl & NAND_NCE)
+                       *nCE |= 0x0004;
+               if (ctrl & NAND_CLE)
+                       IO_ADDR_W |= SET_CLE;
+               if (ctrl & NAND_ALE)
+                       IO_ADDR_W |= SET_ALE;
 
-static u8 nand_read_byte(struct mtd_info *mtdinfo)
-{
-       struct nand_chip *this = mtdinfo->priv;
-       return (u8) (*((volatile u8 *)this->IO_ADDR_R));
-}
+               this->IO_ADDR_W = (void *)IO_ADDR_W;
+       }
 
-static int nand_dev_ready(struct mtd_info *mtdinfo)
-{
-       return 1;
+       if (cmd != NAND_CMD_NONE)
+               writeb(cmd, this->IO_ADDR_W);
 }
 
 int board_nand_init(struct nand_chip *nand)
 {
        volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
 
-       *((volatile u16 *)CONFIG_SYS_LATCH_ADDR) |= 0x0004;
-
-       /* set up pin configuration */
+       /*
+        * set up pin configuration - enabled 2nd output buffer's signals
+        * (nand_ngpio - nCE USB1/2_PWR_EN, LATCH_GPIOs, LCD_VEEEN, etc)
+        * to use nCE signal
+        */
        gpio->par_timer &= ~GPIO_PAR_TIN3_TIN3;
        gpio->pddr_timer |= 0x08;
        gpio->ppd_timer |= 0x08;
@@ -95,9 +81,6 @@ int board_nand_init(struct nand_chip *nand)
        nand->chip_delay = 50;
        nand->ecc.mode = NAND_ECC_SOFT;
        nand->cmd_ctrl = nand_hwcontrol;
-       nand->read_byte = nand_read_byte;
-       nand->write_byte = nand_write_byte;
-       nand->dev_ready = nand_dev_ready;
 
        return 0;
 }

diff --git a/board/freescale/m5373evb/nand.c b/board/freescale/m5373evb/nand.c
index d01b819..3ebef05 100644 (file)
--- a/board/freescale/m5373evb/nand.c
+++ b/board/freescale/m5373evb/nand.c
@@ -41,19 +41,21 @@ DECLARE_GLOBAL_DATA_PTR;
 static void nand_hwcontrol(struct mtd_info *mtdinfo, int cmd, unsigned int ctrl)
 {
        struct nand_chip *this = mtdinfo->priv;
-       volatile fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS;
-       u32 nand_baseaddr = (u32) this->IO_ADDR_W;
+       volatile u16 *nCE = (u16 *) CONFIG_SYS_LATCH_ADDR;
 
        if (ctrl & NAND_CTRL_CHANGE) {
                ulong IO_ADDR_W = (ulong) this->IO_ADDR_W;
-               IO_ADDR_W &= ~(SET_ALE | SE_CLE);
 
+               IO_ADDR_W &= ~(SET_ALE | SET_CLE);
+               *nCE &= 0xFFFB;
+
+               if (ctrl & NAND_NCE)
+                       *nCE |= 0x0004;
                if (ctrl & NAND_CLE)
                        IO_ADDR_W |= SET_CLE;
                if (ctrl & NAND_ALE)
                        IO_ADDR_W |= SET_ALE;
 
-               at91_set_gpio_value(AT91_PIN_PD15, !(ctrl & NAND_NCE));
                this->IO_ADDR_W = (void *)IO_ADDR_W;
 
        }
@@ -67,10 +69,13 @@ int board_nand_init(struct nand_chip *nand)
        volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
        volatile fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS;
 
-       *((volatile u16 *)CONFIG_SYS_LATCH_ADDR) |= 0x0004;
        fbcs->csmr2 &= ~FBCS_CSMR_WP;
 
-       /* set up pin configuration */
+       /*
+        * set up pin configuration - enabled 2nd output buffer's signals
+        * (nand_ngpio - nCE USB1/2_PWR_EN, LATCH_GPIOs, LCD_VEEEN, etc)
+        * to use nCE signal
+        */
        gpio->par_timer &= ~GPIO_PAR_TIN3_TIN3;
        gpio->pddr_timer |= 0x08;
        gpio->ppd_timer |= 0x08;