Indexes->repairIndexesInRange(MBB, Begin, End);
+ // Make sure a live interval exists for all register operands in the range.
+ SmallVector<Register> RegsToRepair(OrigRegs.begin(), OrigRegs.end());
for (MachineBasicBlock::iterator I = End; I != Begin;) {
--I;
MachineInstr &MI = *I;
for (MachineInstr::const_mop_iterator MOI = MI.operands_begin(),
MOE = MI.operands_end();
MOI != MOE; ++MOI) {
- if (MOI->isReg() && Register::isVirtualRegister(MOI->getReg()) &&
- !hasInterval(MOI->getReg())) {
- createAndComputeVirtRegInterval(MOI->getReg());
+ if (MOI->isReg() && MOI->getReg().isVirtual()) {
+ Register Reg = MOI->getReg();
+ // If the new instructions refer to subregs but the old instructions did
+ // not, throw away any old live interval so it will be recomputed with
+ // subranges.
+ if (MOI->getSubReg() && hasInterval(Reg) &&
+ !getInterval(Reg).hasSubRanges() &&
+ MRI->shouldTrackSubRegLiveness(Reg))
+ removeInterval(Reg);
+ if (!hasInterval(Reg)) {
+ createAndComputeVirtRegInterval(Reg);
+ // Don't bother to repair a freshly calculated live interval.
+ erase_value(RegsToRepair, Reg);
+ }
}
}
}
- for (Register Reg : OrigRegs) {
+ for (Register Reg : RegsToRepair) {
if (!Reg.isVirtual())
continue;
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple amdgcn-amd-amdhsa -mcpu=gfx900 < %s | FileCheck --check-prefix=GCN %s
+; RUN: llc -mtriple amdgcn-amd-amdhsa -mcpu=gfx900 -early-live-intervals -verify-machineinstrs < %s | FileCheck --check-prefix=GCN %s
define weak_odr amdgpu_kernel void @test_mul24_knownbits_kernel(float addrspace(1)* %p) #4 {
; GCN-LABEL: test_mul24_knownbits_kernel:
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -march=hexagon < %s | FileCheck %s
+; RUN: llc -march=hexagon -early-live-intervals -verify-machineinstrs < %s | FileCheck %s
target datalayout = "e-m:e-p:32:32:32-a:0-n16:32-i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048"
target triple = "hexagon"
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -verify-machineinstrs -mattr=+mve %s -o - | FileCheck %s
+; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -verify-machineinstrs -mattr=+mve %s -early-live-intervals -verify-machineinstrs -o - | FileCheck %s
define arm_aapcs_vfpcc <2 x i64> @ctlz_2i64_0_t(<2 x i64> %src){
; CHECK-LABEL: ctlz_2i64_0_t: