arm64: dts: renesas: r8a779f0: Fix HSCIF "brg_int" clock

[ Upstream commit a5101ef18b4d0751588f61d939694bad183cc240 ]

As serial communication requires a clean clock signal, the High Speed
Serial Communication Interfaces with FIFO (HSCIF) are clocked by a clock
that is not affected by Spread Spectrum or Fractional Multiplication.

Hence change the clock input for the HSCIF Baud Rate Generator internal
clock from the S0D3_PER clock to the SASYNCPERD1 clock (which has the
same clock rate), cfr. R-Car S4-8 Hardware User's Manual rev. 0.81.

Fixes: 01a787f78bfd ("arm64: dts: renesas: r8a779f0: Add HSCIF nodes")
Reported-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Link: https://lore.kernel.org/r/20221103143440.46449-4-wsa+renesas@sang-engineering.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Sasha Levin <sashal@kernel.org>

diff --git a/arch/arm64/boot/dts/renesas/r8a779f0.dtsi b/arch/arm64/boot/dts/renesas/r8a779f0.dtsi
index c2f152b..3be577d 100644 (file)
--- a/arch/arm64/boot/dts/renesas/r8a779f0.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a779f0.dtsi
@@ -577,7 +577,7 @@
                        reg = <0 0xe6540000 0 0x60>;
                        interrupts = <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>;
                        clocks = <&cpg CPG_MOD 514>,
-                                <&cpg CPG_CORE R8A779F0_CLK_S0D3>,
+                                <&cpg CPG_CORE R8A779F0_CLK_SASYNCPERD1>,
                                 <&scif_clk>;
                        clock-names = "fck", "brg_int", "scif_clk";
                        dmas = <&dmac0 0x31>, <&dmac0 0x30>,
@@ -594,7 +594,7 @@
                        reg = <0 0xe6550000 0 0x60>;
                        interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
                        clocks = <&cpg CPG_MOD 515>,
-                                <&cpg CPG_CORE R8A779F0_CLK_S0D3>,
+                                <&cpg CPG_CORE R8A779F0_CLK_SASYNCPERD1>,
                                 <&scif_clk>;
                        clock-names = "fck", "brg_int", "scif_clk";
                        dmas = <&dmac0 0x33>, <&dmac0 0x32>,
@@ -611,7 +611,7 @@
                        reg = <0 0xe6560000 0 0x60>;
                        interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>;
                        clocks = <&cpg CPG_MOD 516>,
-                                <&cpg CPG_CORE R8A779F0_CLK_S0D3>,
+                                <&cpg CPG_CORE R8A779F0_CLK_SASYNCPERD1>,
                                 <&scif_clk>;
                        clock-names = "fck", "brg_int", "scif_clk";
                        dmas = <&dmac0 0x35>, <&dmac0 0x34>,
@@ -628,7 +628,7 @@
                        reg = <0 0xe66a0000 0 0x60>;
                        interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>;
                        clocks = <&cpg CPG_MOD 517>,
-                                <&cpg CPG_CORE R8A779F0_CLK_S0D3>,
+                                <&cpg CPG_CORE R8A779F0_CLK_SASYNCPERD1>,
                                 <&scif_clk>;
                        clock-names = "fck", "brg_int", "scif_clk";
                        dmas = <&dmac0 0x37>, <&dmac0 0x36>,