#if !defined(_TARGET_64BIT_)
//------------------------------------------------------------------------
-// genIntToIntCast: Generate code for long to int casts on x86.
+// genLongToIntCast: Generate code for long to int casts on x86.
//
// Arguments:
// cast - The GT_CAST node
GenTreePtr castOp = treeNode->gtCast.CastOp();
var_types srcType = genActualType(castOp->TypeGet());
+ noway_assert(genTypeSize(srcType) >= 4);
-#if !defined(_TARGET_64BIT_)
+#ifdef _TARGET_X86_
if (varTypeIsLong(srcType))
{
genLongToIntCast(treeNode);
return;
}
-#endif // !defined(_TARGET_64BIT_)
+#endif // _TARGET_X86_
regNumber targetReg = treeNode->gtRegNum;
regNumber sourceReg = castOp->gtRegNum;
}
bool requiresOverflowCheck = false;
- bool needAndAfter = false;
assert(genIsValidIntReg(targetReg));
assert(genIsValidIntReg(sourceReg));
- instruction ins = INS_invalid;
- emitAttr size = EA_UNKNOWN;
+ instruction ins = INS_invalid;
+ emitAttr srcSize = EA_ATTR(genTypeSize(srcType));
+ emitAttr dstSize = EA_ATTR(genTypeSize(dstType));
- if (genTypeSize(srcType) < genTypeSize(dstType))
+ if (srcSize < dstSize)
{
// Widening cast
-
// Is this an Overflow checking cast?
// We only need to handle one case, as the other casts can never overflow.
// cast from TYP_INT to TYP_ULONG
if (treeNode->gtOverflow() && (srcType == TYP_INT) && (dstType == TYP_ULONG))
{
requiresOverflowCheck = true;
- size = EA_ATTR(genTypeSize(srcType));
ins = INS_mov;
}
else
{
- // we need the source size
- size = EA_ATTR(genTypeSize(srcType));
- noway_assert(size < EA_PTRSIZE);
+ noway_assert(srcSize < EA_PTRSIZE);
ins = ins_Move_Extend(srcType, castOp->InReg());
64-bit, and a regular 32-bit mov clears the high 32 bits (like the non-existant movzxd),
but for a sign extension from TYP_INT to TYP_LONG, we need to use movsxd opcode.
*/
- if (!isUnsignedSrc && !isUnsignedDst && (size == EA_4BYTE) && (genTypeSize(dstType) > EA_4BYTE))
+ if (!isUnsignedSrc && !isUnsignedDst)
{
#ifdef _TARGET_X86_
NYI_X86("Cast to 64 bit for x86/RyuJIT");
ins = INS_movsxd;
#endif // !_TARGET_X86_
}
-
- /*
- Special case: for a cast of byte to char we first
- have to expand the byte (w/ sign extension), then
- mask off the high bits.
- Use 'movsx' followed by 'and'
- */
- if (!isUnsignedSrc && isUnsignedDst && (genTypeSize(dstType) < EA_4BYTE))
- {
- noway_assert(genTypeSize(dstType) == EA_2BYTE && size == EA_1BYTE);
- needAndAfter = true;
- }
}
}
else
{
// Narrowing cast, or sign-changing cast
- noway_assert(genTypeSize(srcType) >= genTypeSize(dstType));
+ noway_assert(srcSize >= dstSize);
// Is this an Overflow checking cast?
if (treeNode->gtOverflow())
{
requiresOverflowCheck = true;
- size = EA_ATTR(genTypeSize(srcType));
ins = INS_mov;
}
else
{
- size = EA_ATTR(genTypeSize(dstType));
- ins = ins_Move_Extend(dstType, castOp->InReg());
+ ins = ins_Move_Extend(dstType, castOp->InReg());
}
}
if (signCheckOnly)
{
// We only need to check for a negative value in sourceReg
- inst_RV_IV(INS_cmp, sourceReg, 0, size);
+ inst_RV_IV(INS_cmp, sourceReg, 0, srcSize);
genJumpToThrowHlpBlk(EJ_jl, SCK_OVERFLOW);
}
else
{
regNumber tmpReg = treeNode->GetSingleTempReg();
inst_RV_RV(INS_mov, tmpReg, sourceReg, TYP_LONG); // Move the 64-bit value to a writeable temp reg
- inst_RV_SH(INS_SHIFT_RIGHT_LOGICAL, size, tmpReg, 32); // Shift right by 32 bits
- genJumpToThrowHlpBlk(EJ_jne, SCK_OVERFLOW); // Throw if result shift is non-zero
+ inst_RV_SH(INS_SHIFT_RIGHT_LOGICAL, srcSize, tmpReg, 32); // Shift right by 32 bits
+ genJumpToThrowHlpBlk(EJ_jne, SCK_OVERFLOW); // Throw if result shift is non-zero
}
else
{
noway_assert(typeMask != 0);
- inst_RV_IV(INS_TEST, sourceReg, typeMask, size);
+ inst_RV_IV(INS_TEST, sourceReg, typeMask, srcSize);
genJumpToThrowHlpBlk(EJ_jne, SCK_OVERFLOW);
}
}
noway_assert((typeMin != 0) && (typeMax != 0));
- inst_RV_IV(INS_cmp, sourceReg, typeMax, size);
+ inst_RV_IV(INS_cmp, sourceReg, typeMax, srcSize);
genJumpToThrowHlpBlk(EJ_jg, SCK_OVERFLOW);
// Compare with the MIN
- inst_RV_IV(INS_cmp, sourceReg, typeMin, size);
+ inst_RV_IV(INS_cmp, sourceReg, typeMin, srcSize);
genJumpToThrowHlpBlk(EJ_jl, SCK_OVERFLOW);
}
}
// On amd64, we can hit this path for a same-register
// 4-byte to 8-byte widening conversion, and need to
// emit the instruction to set the high bits correctly.
- || (EA_ATTR(genTypeSize(dstType)) == EA_8BYTE && EA_ATTR(genTypeSize(srcType)) == EA_4BYTE)
+ || (dstSize == EA_8BYTE && srcSize == EA_4BYTE)
#endif // _TARGET_AMD64_
)
- inst_RV_RV(ins, targetReg, sourceReg, srcType, size);
+ inst_RV_RV(ins, targetReg, sourceReg, srcType, srcSize);
}
else // non-overflow checking cast
{
- noway_assert(size < EA_PTRSIZE || srcType == dstType);
-
// We may have code transformations that result in casts where srcType is the same as dstType.
// e.g. Bug 824281, in which a comma is split by the rationalizer, leaving an assignment of a
// long constant to a long lclVar.
ins = INS_mov;
}
/* Is the value sitting in a non-byte-addressable register? */
- else if (castOp->InReg() && (size == EA_1BYTE) && !isByteReg(sourceReg))
+ else if (castOp->InReg() && (dstSize == EA_1BYTE) && !isByteReg(sourceReg))
{
if (isUnsignedDst)
{
/* Generate "mov targetReg, castOp->gtReg */
if (targetReg != sourceReg)
{
- inst_RV_RV(INS_mov, targetReg, sourceReg, srcType);
+ inst_RV_RV(INS_mov, targetReg, sourceReg, srcType, srcSize);
}
}
if (ins == INS_AND)
{
- noway_assert((needAndAfter == false) && isUnsignedDst);
+ noway_assert(isUnsignedDst);
/* Generate "and reg, MASK */
unsigned fillPattern;
- if (size == EA_1BYTE)
+ if (dstSize == EA_1BYTE)
{
fillPattern = 0xff;
}
- else if (size == EA_2BYTE)
+ else if (dstSize == EA_2BYTE)
{
fillPattern = 0xffff;
}
#ifdef _TARGET_AMD64_
else if (ins == INS_movsxd)
{
- noway_assert(!needAndAfter);
- inst_RV_RV(ins, targetReg, sourceReg, srcType, size);
+ inst_RV_RV(ins, targetReg, sourceReg, srcType, srcSize);
}
#endif // _TARGET_AMD64_
else if (ins == INS_mov)
{
- noway_assert(!needAndAfter);
if (targetReg != sourceReg
#ifdef _TARGET_AMD64_
// On amd64, 'mov' is the opcode used to zero-extend from
// 4 bytes to 8 bytes.
- || (EA_ATTR(genTypeSize(dstType)) == EA_8BYTE && EA_ATTR(genTypeSize(srcType)) == EA_4BYTE)
+ || (dstSize == EA_8BYTE && srcSize == EA_4BYTE)
#endif // _TARGET_AMD64_
)
{
- inst_RV_RV(ins, targetReg, sourceReg, srcType, size);
+ inst_RV_RV(ins, targetReg, sourceReg, srcType, srcSize);
}
}
else
{
noway_assert(ins == INS_movsx || ins == INS_movzx);
+ noway_assert(srcSize >= dstSize);
/* Generate "mov targetReg, castOp->gtReg */
- inst_RV_RV(ins, targetReg, sourceReg, srcType, size);
-
- /* Mask off high bits for cast from byte to char */
- if (needAndAfter)
- {
- noway_assert(genTypeSize(dstType) == 2 && ins == INS_movsx);
- inst_RV_IV(INS_AND, targetReg, 0xFFFF, EA_4BYTE);
- }
+ inst_RV_RV(ins, targetReg, sourceReg, srcType, dstSize);
}
}