PCI: xilinx: Check for MSI interrupt flag before handling as INTx

Occasionally both MSI and INTx bits in the interrupt decode register are
set at once by the Xilinx AXI PCIe Bridge, so the MSI flag in the interrupt
message should be checked to ensure that the correct handler is used.

If this check is not in place and the interrupt message type is MSI, the
INTx handler will be used erroneously when both type bits are set.  This
will also be followed by a second read of the message FIFO, which can
result in the function returning early and the interrupt decode register
not being cleared if the FIFO is now empty.

Signed-off-by: Russell Joyce <russell.joyce@york.ac.uk>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>

diff --git a/drivers/pci/host/pcie-xilinx.c b/drivers/pci/host/pcie-xilinx.c
index f1a06a0..dcb9b57 100644 (file)
--- a/drivers/pci/host/pcie-xilinx.c
+++ b/drivers/pci/host/pcie-xilinx.c
@@ -449,14 +449,17 @@ static irqreturn_t xilinx_pcie_intr_handler(int irq, void *data)
                        return IRQ_HANDLED;
                }
 
-               /* Clear interrupt FIFO register 1 */
-               pcie_write(port, XILINX_PCIE_RPIFR1_ALL_MASK,
-                          XILINX_PCIE_REG_RPIFR1);
-
-               /* Handle INTx Interrupt */
-               val = ((val & XILINX_PCIE_RPIFR1_INTR_MASK) >>
-                       XILINX_PCIE_RPIFR1_INTR_SHIFT) + 1;
-               generic_handle_irq(irq_find_mapping(port->irq_domain, val));
+               if (!(val & XILINX_PCIE_RPIFR1_MSI_INTR)) {
+                       /* Clear interrupt FIFO register 1 */
+                       pcie_write(port, XILINX_PCIE_RPIFR1_ALL_MASK,
+                                  XILINX_PCIE_REG_RPIFR1);
+
+                       /* Handle INTx Interrupt */
+                       val = ((val & XILINX_PCIE_RPIFR1_INTR_MASK) >>
+                               XILINX_PCIE_RPIFR1_INTR_SHIFT) + 1;
+                       generic_handle_irq(irq_find_mapping(port->irq_domain,
+                                                           val));
+               }
        }
 
        if (status & XILINX_PCIE_INTR_MSI) {