%s = select <16 x i1> %sh, <16 x i8> %a, <16 x i8> %b
ret <16 x i8> %s
}
+
+define <16 x i8> @shuffle2src_v16i8(<16 x i8> %src1, <16 x i8> %src2, <16 x i8> %a, <16 x i8> %b) {
+; CHECK-LABEL: shuffle2src_v16i8:
+; CHECK: @ %bb.0: @ %entry
+; CHECK-NEXT: mov r12, sp
+; CHECK-NEXT: vmov d6, r0, r1
+; CHECK-NEXT: vldrw.u32 q2, [r12]
+; CHECK-NEXT: vmov.i8 q0, #0x0
+; CHECK-NEXT: vmov.i8 q1, #0xff
+; CHECK-NEXT: vmov d7, r2, r3
+; CHECK-NEXT: vcmp.i8 eq, q2, zr
+; CHECK-NEXT: add r0, sp, #32
+; CHECK-NEXT: vpsel q2, q1, q0
+; CHECK-NEXT: vcmp.i8 eq, q3, zr
+; CHECK-NEXT: vpsel q0, q1, q0
+; CHECK-NEXT: vmovnt.i16 q2, q0
+; CHECK-NEXT: vldrw.u32 q0, [r0]
+; CHECK-NEXT: add r0, sp, #16
+; CHECK-NEXT: vcmp.i8 ne, q2, zr
+; CHECK-NEXT: vldrw.u32 q1, [r0]
+; CHECK-NEXT: vpsel q0, q1, q0
+; CHECK-NEXT: vmov r0, r1, d0
+; CHECK-NEXT: vmov r2, r3, d1
+; CHECK-NEXT: bx lr
+entry:
+ %c1 = icmp eq <16 x i8> %src1, zeroinitializer
+ %c2 = icmp eq <16 x i8> %src2, zeroinitializer
+ %sh = shufflevector <16 x i1> %c1, <16 x i1> %c2, <16 x i32> <i32 16, i32 0, i32 18, i32 2, i32 20, i32 4, i32 22, i32 6, i32 24, i32 8, i32 26, i32 10, i32 28, i32 12, i32 30, i32 14>
+ %s = select <16 x i1> %sh, <16 x i8> %a, <16 x i8> %b
+ ret <16 x i8> %s
+}
+
+define <8 x i16> @shuffle2src_v8i16(<8 x i16> %src1, <8 x i16> %src2, <8 x i16> %a, <8 x i16> %b) {
+; CHECK-LABEL: shuffle2src_v8i16:
+; CHECK: @ %bb.0: @ %entry
+; CHECK-NEXT: mov r12, sp
+; CHECK-NEXT: vmov d6, r0, r1
+; CHECK-NEXT: vldrw.u32 q2, [r12]
+; CHECK-NEXT: vmov.i8 q0, #0x0
+; CHECK-NEXT: vmov.i8 q1, #0xff
+; CHECK-NEXT: vmov d7, r2, r3
+; CHECK-NEXT: vcmp.i16 eq, q2, zr
+; CHECK-NEXT: add r0, sp, #32
+; CHECK-NEXT: vpsel q2, q1, q0
+; CHECK-NEXT: vcmp.i16 eq, q3, zr
+; CHECK-NEXT: vpsel q0, q1, q0
+; CHECK-NEXT: vmovnt.i32 q2, q0
+; CHECK-NEXT: vldrw.u32 q0, [r0]
+; CHECK-NEXT: add r0, sp, #16
+; CHECK-NEXT: vcmp.i16 ne, q2, zr
+; CHECK-NEXT: vldrw.u32 q1, [r0]
+; CHECK-NEXT: vpsel q0, q1, q0
+; CHECK-NEXT: vmov r0, r1, d0
+; CHECK-NEXT: vmov r2, r3, d1
+; CHECK-NEXT: bx lr
+entry:
+ %c1 = icmp eq <8 x i16> %src1, zeroinitializer
+ %c2 = icmp eq <8 x i16> %src2, zeroinitializer
+ %sh = shufflevector <8 x i1> %c1, <8 x i1> %c2, <8 x i32> <i32 8, i32 0, i32 10, i32 2, i32 12, i32 4, i32 14, i32 6>
+ %s = select <8 x i1> %sh, <8 x i16> %a, <8 x i16> %b
+ ret <8 x i16> %s
+}
+
+define <4 x i32> @shuffle2src_v4i32(<4 x i32> %src1, <4 x i32> %src2, <4 x i32> %a, <4 x i32> %b) {
+; CHECK-LABEL: shuffle2src_v4i32:
+; CHECK: @ %bb.0: @ %entry
+; CHECK-NEXT: mov r12, sp
+; CHECK-NEXT: vmov d6, r0, r1
+; CHECK-NEXT: vldrw.u32 q2, [r12]
+; CHECK-NEXT: vmov.i8 q0, #0x0
+; CHECK-NEXT: vmov.i8 q1, #0xff
+; CHECK-NEXT: vmov d7, r2, r3
+; CHECK-NEXT: vcmp.i32 eq, q2, zr
+; CHECK-NEXT: add r0, sp, #32
+; CHECK-NEXT: vpsel q2, q1, q0
+; CHECK-NEXT: vcmp.i32 eq, q3, zr
+; CHECK-NEXT: vpsel q0, q1, q0
+; CHECK-NEXT: vmov.f32 s9, s0
+; CHECK-NEXT: vmov.f32 s11, s2
+; CHECK-NEXT: vldrw.u32 q0, [r0]
+; CHECK-NEXT: add r0, sp, #16
+; CHECK-NEXT: vcmp.i32 ne, q2, zr
+; CHECK-NEXT: vldrw.u32 q1, [r0]
+; CHECK-NEXT: vpsel q0, q1, q0
+; CHECK-NEXT: vmov r0, r1, d0
+; CHECK-NEXT: vmov r2, r3, d1
+; CHECK-NEXT: bx lr
+entry:
+ %c1 = icmp eq <4 x i32> %src1, zeroinitializer
+ %c2 = icmp eq <4 x i32> %src2, zeroinitializer
+ %sh = shufflevector <4 x i1> %c1, <4 x i1> %c2, <4 x i32> <i32 4, i32 0, i32 6, i32 2>
+ %s = select <4 x i1> %sh, <4 x i32> %a, <4 x i32> %b
+ ret <4 x i32> %s
+}
+
+define <2 x i64> @shuffle2src_v2i64(<2 x i64> %src1, <2 x i64> %src2, <2 x i64> %a, <2 x i64> %b) {
+; CHECK-LABEL: shuffle2src_v2i64:
+; CHECK: @ %bb.0: @ %entry
+; CHECK-NEXT: ldrd r2, r3, [sp]
+; CHECK-NEXT: orrs r2, r3
+; CHECK-NEXT: mov.w r3, #0
+; CHECK-NEXT: csetm r2, eq
+; CHECK-NEXT: orrs r0, r1
+; CHECK-NEXT: bfi r3, r2, #0, #8
+; CHECK-NEXT: csetm r0, eq
+; CHECK-NEXT: bfi r3, r0, #8, #8
+; CHECK-NEXT: add r0, sp, #32
+; CHECK-NEXT: vldrw.u32 q0, [r0]
+; CHECK-NEXT: add r0, sp, #16
+; CHECK-NEXT: vldrw.u32 q1, [r0]
+; CHECK-NEXT: vmsr p0, r3
+; CHECK-NEXT: vpsel q0, q1, q0
+; CHECK-NEXT: vmov r0, r1, d0
+; CHECK-NEXT: vmov r2, r3, d1
+; CHECK-NEXT: bx lr
+entry:
+ %c1 = icmp eq <2 x i64> %src1, zeroinitializer
+ %c2 = icmp eq <2 x i64> %src2, zeroinitializer
+ %sh = shufflevector <2 x i1> %c1, <2 x i1> %c2, <2 x i32> <i32 2, i32 0>
+ %s = select <2 x i1> %sh, <2 x i64> %a, <2 x i64> %b
+ ret <2 x i64> %s
+}