'&' for the letter `d' in an op code, but only on the 68040.
'/' for register prefix needed by longlong.h.
'?' for m68k_library_id_string
+ '{' for '{'
+ '}' for '}'
'b' for byte insn (no effect, on the Sun; this is for the ISI).
'd' to force memory addressing to be absolute, not relative.
#define PRINT_OPERAND_PUNCT_VALID_P(CODE) \
((CODE) == '.' || (CODE) == '#' || (CODE) == '-' \
|| (CODE) == '+' || (CODE) == '@' || (CODE) == '!' \
- || (CODE) == '$' || (CODE) == '&' || (CODE) == '/' || (CODE) == '?')
+ || (CODE) == '$' || (CODE) == '&' || (CODE) == '/' || (CODE) == '?' \
+ || (CODE) == '{' || (CODE) == '}')
/* See m68k.c for the m68k specific codes. */
if (REG_P (operands[0]))
{
if (INTVAL (operands[1]) + INTVAL (operands[2]) != 32)
- return "bfins %3,%0{%b2:%b1}";
+ return "bfins %3,%0%{%b2:%b1%}";
}
else
operands[0] = adjust_address (operands[0],
if (REG_P (operands[1]))
{
if (INTVAL (operands[2]) + INTVAL (operands[3]) != 32)
- return "bfextu %1{%b3:%b2},%0";
+ return "bfextu %1%{%b3:%b2%},%0";
}
else
operands[1]
if (REG_P (operands[1]))
{
if (INTVAL (operands[2]) + INTVAL (operands[3]) != 32)
- return "bfexts %1{%b3:%b2},%0";
+ return "bfexts %1%{%b3:%b2%},%0";
}
else
operands[1]
(match_operand:SI 2 "nonmemory_operand" "dn")
(match_operand:SI 3 "nonmemory_operand" "dn")))]
"TARGET_68020 && TARGET_BITFIELD"
- "bfexts %1{%b3:%b2},%0")
+ "bfexts %1%{%b3:%b2%},%0")
(define_expand "extzv"
[(set (match_operand:SI 0 "register_operand" "")
{
CC_STATUS_INIT;
}
- return "bfextu %1{%b3:%b2},%0";
+ return "bfextu %1%{%b3:%b2%},%0";
})
(define_insn ""
&& (~ INTVAL (operands[3]) & ((1 << INTVAL (operands[1]))- 1)) == 0))"
{
CC_STATUS_INIT;
- return "bfchg %0{%b2:%b1}";
+ return "bfchg %0%{%b2:%b1%}";
})
(define_insn ""
"TARGET_68020 && TARGET_BITFIELD"
{
CC_STATUS_INIT;
- return "bfclr %0{%b2:%b1}";
+ return "bfclr %0%{%b2:%b1%}";
})
(define_insn ""
"TARGET_68020 && TARGET_BITFIELD"
{
CC_STATUS_INIT;
- return "bfset %0{%b2:%b1}";
+ return "bfset %0%{%b2:%b1%}";
})
(define_expand "insv"
(match_operand:SI 2 "nonmemory_operand" "dn"))
(match_operand:SI 3 "register_operand" "d"))]
"TARGET_68020 && TARGET_BITFIELD"
- "bfins %3,%0{%b2:%b1}")
+ "bfins %3,%0%{%b2:%b1%}")
;; Now recognize bit-field insns that operate on registers
;; (or at least were intended to do so).
(match_operand:SI 2 "const_int_operand" "n")
(match_operand:SI 3 "const_int_operand" "n")))]
"TARGET_68020 && TARGET_BITFIELD"
- "bfexts %1{%b3:%b2},%0")
+ "bfexts %1%{%b3:%b2%},%0")
(define_insn ""
[(set (match_operand:SI 0 "nonimmediate_operand" "=d")
{
CC_STATUS_INIT;
}
- return "bfextu %1{%b3:%b2},%0";
+ return "bfextu %1%{%b3:%b2%},%0";
})
(define_insn ""
"TARGET_68020 && TARGET_BITFIELD"
{
CC_STATUS_INIT;
- return "bfclr %0{%b2:%b1}";
+ return "bfclr %0%{%b2:%b1%}";
})
(define_insn ""
"TARGET_68020 && TARGET_BITFIELD"
{
CC_STATUS_INIT;
- return "bfset %0{%b2:%b1}";
+ return "bfset %0%{%b2:%b1%}";
})
(define_insn ""
&& INTVAL (operands[1]) == 24 && INTVAL (operands[2]) == 8)
return "move%.b %3,%0";
#endif
- return "bfins %3,%0{%b2:%b1}";
+ return "bfins %3,%0%{%b2:%b1%}";
})
\f
;; Special patterns for optimizing bit-field instructions.
}
if (INTVAL (operands[1]) != 32)
cc_status.flags = CC_NOT_NEGATIVE;
- return "bftst %0{%b2:%b1}";
+ return "bftst %0%{%b2:%b1%}";
})
}
if (INTVAL (operands[1]) != 32)
cc_status.flags = CC_NOT_NEGATIVE;
- return "bftst %0{%b2:%b1}";
+ return "bftst %0%{%b2:%b1%}";
})
\f
(define_insn "scc0_di"