gbe_program prog = ker->program->opaque;
const int32_t arg_n = interp_kernel_get_arg_num(ker->opaque);
size_t global_const_size = interp_program_get_global_constant_size(prog);
- aligned_size = raw_size = global_const_size;
+ raw_size = global_const_size;
+ // Surface state need 4 byte alignment, and Constant argument's buffer size
+ // have align to 4 byte when alloc, so align global constant size to 4 can
+ // ensure the finally aligned_size align to 4.
+ aligned_size = ALIGN(raw_size, 4);
/* Reserve 8 bytes to get rid of 0 address */
if(global_const_size == 0) aligned_size = 8;
ss0->ss0.surface_type = I965_SURFACE_BUFFER;
ss0->ss0.surface_format = format;
ss0->ss2.width = s & 0x7f; /* bits 6:0 of sz */
+ // Per bspec, I965_SURFACE_BUFFER and RAW format, size must be a multiple of 4 byte.
+ if(format == I965_SURFACEFORMAT_RAW)
+ assert((ss0->ss2.width & 0x03) == 3);
ss0->ss2.height = (s >> 7) & 0x3fff; /* bits 20:7 of sz */
ss0->ss3.depth = (s >> 21) & 0x3ff; /* bits 30:21 of sz */
ss0->ss5.cache_control = cl_gpgpu_get_cache_ctrl();
ss0->ss7.shader_a = I965_SURCHAN_SELECT_ALPHA;
}
ss0->ss2.width = s & 0x7f; /* bits 6:0 of sz */
+ // Per bspec, I965_SURFACE_BUFFER and RAW format, size must be a multiple of 4 byte.
+ if(format == I965_SURFACEFORMAT_RAW)
+ assert((ss0->ss2.width & 0x03) == 3);
ss0->ss2.height = (s >> 7) & 0x3fff; /* bits 20:7 of sz */
ss0->ss3.depth = (s >> 21) & 0x3ff; /* bits 30:21 of sz */
ss0->ss5.cache_control = cl_gpgpu_get_cache_ctrl();
ss0->ss7.shader_channel_select_alpha = I965_SURCHAN_SELECT_ALPHA;
}
ss0->ss2.width = s & 0x7f; /* bits 6:0 of sz */
- assert(ss0->ss2.width & 0x03);
+ // Per bspec, I965_SURFACE_BUFFER and RAW format, size must be a multiple of 4 byte.
+ if(format == I965_SURFACEFORMAT_RAW)
+ assert((ss0->ss2.width & 0x03) == 3);
ss0->ss2.height = (s >> 7) & 0x3fff; /* bits 20:7 of sz */
ss0->ss3.depth = (s >> 21) & 0x3ff; /* bits 30:21 of sz */
ss0->ss1.mem_obj_ctrl_state = cl_gpgpu_get_cache_ctrl();