net/mlx5: Lag, set match mask according to the traffic type bitmap

Set the related bits in the match definer mask according to the
TT mapping.
This mask will be used to create the match definers.

Signed-off-by: Maor Gottlieb <maorg@nvidia.com>
Reviewed-by: Mark Bloch <mbloch@nvidia.com>
Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>

diff --git a/drivers/net/ethernet/mellanox/mlx5/core/lag/port_sel.c b/drivers/net/ethernet/mellanox/mlx5/core/lag/port_sel.c
index 7b4ad49..6095f10 100644 (file)
--- a/drivers/net/ethernet/mellanox/mlx5/core/lag/port_sel.c
+++ b/drivers/net/ethernet/mellanox/mlx5/core/lag/port_sel.c
@@ -4,6 +4,188 @@
 #include <linux/netdevice.h>
 #include "lag.h"
 
+static int mlx5_lag_set_definer_inner(u32 *match_definer_mask,
+                                     enum mlx5_traffic_types tt)
+{
+       int format_id;
+       u8 *ipv6;
+
+       switch (tt) {
+       case MLX5_TT_IPV4_UDP:
+       case MLX5_TT_IPV4_TCP:
+               format_id = 23;
+               MLX5_SET_TO_ONES(match_definer_format_23, match_definer_mask,
+                                inner_l4_sport);
+               MLX5_SET_TO_ONES(match_definer_format_23, match_definer_mask,
+                                inner_l4_dport);
+               MLX5_SET_TO_ONES(match_definer_format_23, match_definer_mask,
+                                inner_ip_src_addr);
+               MLX5_SET_TO_ONES(match_definer_format_23, match_definer_mask,
+                                inner_ip_dest_addr);
+               break;
+       case MLX5_TT_IPV4:
+               format_id = 23;
+               MLX5_SET_TO_ONES(match_definer_format_23, match_definer_mask,
+                                inner_l3_type);
+               MLX5_SET_TO_ONES(match_definer_format_23, match_definer_mask,
+                                inner_dmac_47_16);
+               MLX5_SET_TO_ONES(match_definer_format_23, match_definer_mask,
+                                inner_dmac_15_0);
+               MLX5_SET_TO_ONES(match_definer_format_23, match_definer_mask,
+                                inner_smac_47_16);
+               MLX5_SET_TO_ONES(match_definer_format_23, match_definer_mask,
+                                inner_smac_15_0);
+               MLX5_SET_TO_ONES(match_definer_format_23, match_definer_mask,
+                                inner_ip_src_addr);
+               MLX5_SET_TO_ONES(match_definer_format_23, match_definer_mask,
+                                inner_ip_dest_addr);
+               break;
+       case MLX5_TT_IPV6_TCP:
+       case MLX5_TT_IPV6_UDP:
+               format_id = 31;
+               MLX5_SET_TO_ONES(match_definer_format_31, match_definer_mask,
+                                inner_l4_sport);
+               MLX5_SET_TO_ONES(match_definer_format_31, match_definer_mask,
+                                inner_l4_dport);
+               ipv6 = MLX5_ADDR_OF(match_definer_format_31, match_definer_mask,
+                                   inner_ip_dest_addr);
+               memset(ipv6, 0xff, 16);
+               ipv6 = MLX5_ADDR_OF(match_definer_format_31, match_definer_mask,
+                                   inner_ip_src_addr);
+               memset(ipv6, 0xff, 16);
+               break;
+       case MLX5_TT_IPV6:
+               format_id = 32;
+               ipv6 = MLX5_ADDR_OF(match_definer_format_32, match_definer_mask,
+                                   inner_ip_dest_addr);
+               memset(ipv6, 0xff, 16);
+               ipv6 = MLX5_ADDR_OF(match_definer_format_32, match_definer_mask,
+                                   inner_ip_src_addr);
+               memset(ipv6, 0xff, 16);
+               MLX5_SET_TO_ONES(match_definer_format_32, match_definer_mask,
+                                inner_dmac_47_16);
+               MLX5_SET_TO_ONES(match_definer_format_32, match_definer_mask,
+                                inner_dmac_15_0);
+               MLX5_SET_TO_ONES(match_definer_format_32, match_definer_mask,
+                                inner_smac_47_16);
+               MLX5_SET_TO_ONES(match_definer_format_32, match_definer_mask,
+                                inner_smac_15_0);
+               break;
+       default:
+               format_id = 23;
+               MLX5_SET_TO_ONES(match_definer_format_23, match_definer_mask,
+                                inner_l3_type);
+               MLX5_SET_TO_ONES(match_definer_format_23, match_definer_mask,
+                                inner_dmac_47_16);
+               MLX5_SET_TO_ONES(match_definer_format_23, match_definer_mask,
+                                inner_dmac_15_0);
+               MLX5_SET_TO_ONES(match_definer_format_23, match_definer_mask,
+                                inner_smac_47_16);
+               MLX5_SET_TO_ONES(match_definer_format_23, match_definer_mask,
+                                inner_smac_15_0);
+               break;
+       }
+
+       return format_id;
+}
+
+static int mlx5_lag_set_definer(u32 *match_definer_mask,
+                               enum mlx5_traffic_types tt, bool tunnel,
+                               enum netdev_lag_hash hash)
+{
+       int format_id;
+       u8 *ipv6;
+
+       if (tunnel)
+               return mlx5_lag_set_definer_inner(match_definer_mask, tt);
+
+       switch (tt) {
+       case MLX5_TT_IPV4_UDP:
+       case MLX5_TT_IPV4_TCP:
+               format_id = 22;
+               MLX5_SET_TO_ONES(match_definer_format_22, match_definer_mask,
+                                outer_l4_sport);
+               MLX5_SET_TO_ONES(match_definer_format_22, match_definer_mask,
+                                outer_l4_dport);
+               MLX5_SET_TO_ONES(match_definer_format_22, match_definer_mask,
+                                outer_ip_src_addr);
+               MLX5_SET_TO_ONES(match_definer_format_22, match_definer_mask,
+                                outer_ip_dest_addr);
+               break;
+       case MLX5_TT_IPV4:
+               format_id = 22;
+               MLX5_SET_TO_ONES(match_definer_format_22, match_definer_mask,
+                                outer_l3_type);
+               MLX5_SET_TO_ONES(match_definer_format_22, match_definer_mask,
+                                outer_dmac_47_16);
+               MLX5_SET_TO_ONES(match_definer_format_22, match_definer_mask,
+                                outer_dmac_15_0);
+               MLX5_SET_TO_ONES(match_definer_format_22, match_definer_mask,
+                                outer_smac_47_16);
+               MLX5_SET_TO_ONES(match_definer_format_22, match_definer_mask,
+                                outer_smac_15_0);
+               MLX5_SET_TO_ONES(match_definer_format_22, match_definer_mask,
+                                outer_ip_src_addr);
+               MLX5_SET_TO_ONES(match_definer_format_22, match_definer_mask,
+                                outer_ip_dest_addr);
+               break;
+       case MLX5_TT_IPV6_TCP:
+       case MLX5_TT_IPV6_UDP:
+               format_id = 29;
+               MLX5_SET_TO_ONES(match_definer_format_29, match_definer_mask,
+                                outer_l4_sport);
+               MLX5_SET_TO_ONES(match_definer_format_29, match_definer_mask,
+                                outer_l4_dport);
+               ipv6 = MLX5_ADDR_OF(match_definer_format_29, match_definer_mask,
+                                   outer_ip_dest_addr);
+               memset(ipv6, 0xff, 16);
+               ipv6 = MLX5_ADDR_OF(match_definer_format_29, match_definer_mask,
+                                   outer_ip_src_addr);
+               memset(ipv6, 0xff, 16);
+               break;
+       case MLX5_TT_IPV6:
+               format_id = 30;
+               ipv6 = MLX5_ADDR_OF(match_definer_format_30, match_definer_mask,
+                                   outer_ip_dest_addr);
+               memset(ipv6, 0xff, 16);
+               ipv6 = MLX5_ADDR_OF(match_definer_format_30, match_definer_mask,
+                                   outer_ip_src_addr);
+               memset(ipv6, 0xff, 16);
+               MLX5_SET_TO_ONES(match_definer_format_30, match_definer_mask,
+                                outer_dmac_47_16);
+               MLX5_SET_TO_ONES(match_definer_format_30, match_definer_mask,
+                                outer_dmac_15_0);
+               MLX5_SET_TO_ONES(match_definer_format_30, match_definer_mask,
+                                outer_smac_47_16);
+               MLX5_SET_TO_ONES(match_definer_format_30, match_definer_mask,
+                                outer_smac_15_0);
+               break;
+       default:
+               format_id = 0;
+               MLX5_SET_TO_ONES(match_definer_format_0, match_definer_mask,
+                                outer_smac_47_16);
+               MLX5_SET_TO_ONES(match_definer_format_0, match_definer_mask,
+                                outer_smac_15_0);
+
+               if (hash == NETDEV_LAG_HASH_VLAN_SRCMAC) {
+                       MLX5_SET_TO_ONES(match_definer_format_0,
+                                        match_definer_mask,
+                                        outer_first_vlan_vid);
+                       break;
+               }
+
+               MLX5_SET_TO_ONES(match_definer_format_0, match_definer_mask,
+                                outer_ethertype);
+               MLX5_SET_TO_ONES(match_definer_format_0, match_definer_mask,
+                                outer_dmac_47_16);
+               MLX5_SET_TO_ONES(match_definer_format_0, match_definer_mask,
+                                outer_dmac_15_0);
+               break;
+       }
+
+       return format_id;
+}
+
 static void set_tt_map(struct mlx5_lag_port_sel *port_sel,
                       enum netdev_lag_hash hash)
 {