Change display KSEL based on config option CTP_CRYSTAL_38M4.

BZ: 25776

For cloverview+, 19.2 MHz crystal plan to be used. With cloverview A0
38.4 MHz crystal being used. Change display KSEL based on kernel config
option CTP_CRYSTAL_38M4. With 19.2 MHz. HDMI clock needs to be hardcoded
due to some regression, to be fixed later.

Change-Id: I537fae5ea52535e55998e8a86befa1e1a0599f8b
Signed-off-by: Seema Pandit <seema.pandit@intel.com>
Reviewed-on: http://android.intel.com:8080/37305
Reviewed-by: Monroy, German <german.monroy@intel.com>
Reviewed-by: Gao, Bin <bin.gao@intel.com>
Reviewed-by: Hu, Austin <austin.hu@intel.com>
Reviewed-by: Tong, BoX <box.tong@intel.com>
Tested-by: Tong, BoX <box.tong@intel.com>
Reviewed-by: Ai, Ke <ke.ai@intel.com>
Reviewed-by: buildbot <buildbot@intel.com>
Tested-by: buildbot <buildbot@intel.com>

diff --git a/drivers/staging/mrst/drv/psb_intel_display2.c b/drivers/staging/mrst/drv/psb_intel_display2.c
index f145a9b..04a557a 100644 (file)
--- a/drivers/staging/mrst/drv/psb_intel_display2.c
+++ b/drivers/staging/mrst/drv/psb_intel_display2.c
@@ -1855,13 +1855,18 @@ static int mdfld_crtc_mode_set(struct drm_crtc *crtc,
                /* compute bitmask from p1 value */
                dpll |= (1 << (clock.p1 - 2)) << 17;
 
-#if 0 /* 1080p30 & 720p */
-               dpll = 0x00050000;
-               fp = 0x000001be;
+               if (IS_CTP(dev)) {
+#ifndef CONFIG_CTP_CRYSTAL_38M4
+                       dpll = 0x00050000;
+                       fp = 0x000001be;
+#endif
                /* In case clocking issues try value below for CTP.
-               Please keep this one for reference. */
+               Please keep this one for reference. For 38.4 MHz. */
+#if 0 /* 1080p30 & 720p */
                fp = 0x000101be;
 #endif
+               }
+
 #if 0 /* 480p */
                dpll = 0x02010000;
                fp = 0x000000d2;

diff --git a/drivers/staging/mrst/drv/psb_intel_drv.h b/drivers/staging/mrst/drv/psb_intel_drv.h
index f27ddc7..0729cff 100644 (file)
--- a/drivers/staging/mrst/drv/psb_intel_drv.h
+++ b/drivers/staging/mrst/drv/psb_intel_drv.h
@@ -32,7 +32,7 @@
 /* MDFLD MIPI panels only one of them can be set to 1 */
 
 /* MDFLD KSEL only one of them can be set to 1 */ 
-#ifdef CONFIG_DRM_CTP
+#ifdef CONFIG_CTP_CRYSTAL_38M4
 #define KSEL_CRYSTAL_19_ENABLED 0
 #define KSEL_CRYSTAL_38_ENABLED 1
 #else