hdmirx: tl1 hdmirx no interrupt [1/1]

PD#172587

Problem:
1.no interrupt
2.add fsm debug log

Solution:
1.change interrupt id
2.change interrupt source
3.change 6g phy setting
4.add axi clk
5.verify emp pkt data to ddr

Verify:
1.verify on chip

Change-Id: I349439d90a356144b96af4831e03fa0e9e90076b
Signed-off-by: Yong Qin <yong.qin@amlogic.com>

diff --git a/arch/arm/boot/dts/amlogic/tl1_pxp.dts b/arch/arm/boot/dts/amlogic/tl1_pxp.dts
index 7bc0f4b..3ab3a9b 100644 (file)
--- a/arch/arm/boot/dts/amlogic/tl1_pxp.dts
+++ b/arch/arm/boot/dts/amlogic/tl1_pxp.dts
@@ -476,11 +476,12 @@
                pinctrl-0 = <&hdmirx_a_mux &hdmirx_b_mux
                        &hdmirx_c_mux>;
                repeat = <0>;
-               interrupts = <0 56 1>;
+               interrupts = <0 41 1>;
                clocks = <&clkc CLKID_HDMIRX_MODET_COMP>,
                           <&clkc CLKID_HDMIRX_CFG_COMP>,
                           <&clkc CLKID_HDMIRX_ACR_COMP>,
                           <&clkc CLKID_HDMIRX_METER_COMP>,
+                          <&clkc CLKID_HDMIRX_AXI_COMP>,
                           <&xtal>,
                           <&clkc CLKID_FCLK_DIV5>,
                           <&clkc CLKID_FCLK_DIV7>,
@@ -493,6 +494,7 @@
                        "hdmirx_cfg_clk",
                                "hdmirx_acr_ref_clk",
                                "cts_hdmirx_meter_clk",
+                               "cts_hdmi_axi_clk",
                                "xtal",
                                "fclk_div5",
                                "fclk_div7",

diff --git a/arch/arm/boot/dts/amlogic/tl1_t962x2_skt.dts b/arch/arm/boot/dts/amlogic/tl1_t962x2_skt.dts
index b85fb74..bfc3385 100644 (file)
--- a/arch/arm/boot/dts/amlogic/tl1_t962x2_skt.dts
+++ b/arch/arm/boot/dts/amlogic/tl1_t962x2_skt.dts
@@ -723,11 +723,12 @@
                pinctrl-0 = <&hdmirx_a_mux &hdmirx_b_mux
                        &hdmirx_c_mux>;
                repeat = <0>;
-               interrupts = <0 56 1>;
+               interrupts = <0 41 1>;
                clocks = <&clkc CLKID_HDMIRX_MODET_COMP>,
                           <&clkc CLKID_HDMIRX_CFG_COMP>,
                           <&clkc CLKID_HDMIRX_ACR_COMP>,
                           <&clkc CLKID_HDMIRX_METER_COMP>,
+                          <&clkc CLKID_HDMIRX_AXI_COMP>,
                           <&xtal>,
                           <&clkc CLKID_FCLK_DIV5>,
                           <&clkc CLKID_FCLK_DIV7>,
@@ -740,6 +741,7 @@
                        "hdmirx_cfg_clk",
                                "hdmirx_acr_ref_clk",
                                "cts_hdmirx_meter_clk",
+                               "cts_hdmi_axi_clk",
                                "xtal",
                                "fclk_div5",
                                "fclk_div7",

diff --git a/arch/arm/boot/dts/amlogic/tl1_t962x2_x301.dts b/arch/arm/boot/dts/amlogic/tl1_t962x2_x301.dts
index 9eddb40..6784c17 100644 (file)
--- a/arch/arm/boot/dts/amlogic/tl1_t962x2_x301.dts
+++ b/arch/arm/boot/dts/amlogic/tl1_t962x2_x301.dts
@@ -727,11 +727,12 @@
                pinctrl-0 = <&hdmirx_a_mux &hdmirx_b_mux
                        &hdmirx_c_mux>;
                repeat = <0>;
-               interrupts = <0 56 1>;
+               interrupts = <0 41 1>;
                clocks = <&clkc CLKID_HDMIRX_MODET_COMP>,
                           <&clkc CLKID_HDMIRX_CFG_COMP>,
                           <&clkc CLKID_HDMIRX_ACR_COMP>,
                           <&clkc CLKID_HDMIRX_METER_COMP>,
+                          <&clkc CLKID_HDMIRX_AXI_COMP>,
                           <&xtal>,
                           <&clkc CLKID_FCLK_DIV5>,
                           <&clkc CLKID_FCLK_DIV7>,
@@ -744,6 +745,7 @@
                        "hdmirx_cfg_clk",
                                "hdmirx_acr_ref_clk",
                                "cts_hdmirx_meter_clk",
+                               "cts_hdmi_axi_clk",
                                "xtal",
                                "fclk_div5",
                                "fclk_div7",

diff --git a/drivers/amlogic/media/vin/tvin/hdmirx/hdmi_rx_drv.c b/drivers/amlogic/media/vin/tvin/hdmirx/hdmi_rx_drv.c
index d7d4da9..4391a93 100644 (file)
--- a/drivers/amlogic/media/vin/tvin/hdmirx/hdmi_rx_drv.c
+++ b/drivers/amlogic/media/vin/tvin/hdmirx/hdmi_rx_drv.c
@@ -1735,11 +1735,12 @@ void rx_emp_resource_allocate(struct device *dev)
                                        EMP_BUFFER_SIZE >> PAGE_SHIFT, 0);
                if (rx.empbuff.pg_addr) {
                        /* hw access */
-                       /* page to real address*/
+                       /* page to real physical address*/
                        rx.empbuff.p_addr_a =
                                page_to_phys(rx.empbuff.pg_addr);
                        rx.empbuff.p_addr_b =
                                rx.empbuff.p_addr_a + (EMP_BUFFER_SIZE >> 1);
+                       //page_address
                        rx_pr("buffa paddr=0x%x\n", rx.empbuff.p_addr_a);
                        rx_pr("buffb paddr=0x%x\n", rx.empbuff.p_addr_b);
                } else {
@@ -2144,6 +2145,7 @@ static int hdmirx_probe(struct platform_device *pdev)
        }
        #endif
        if (rx.hdmirxdev->data->chip_id == CHIP_ID_TL1) {
+               /*for audio clk measure*/
                hdevp->meter_clk = clk_get(&pdev->dev, "cts_hdmirx_meter_clk");
                if (IS_ERR(hdevp->meter_clk))
                        rx_pr("get cts hdmirx meter clk err\n");
@@ -2153,6 +2155,16 @@ static int hdmirx_probe(struct platform_device *pdev)
                        clk_prepare_enable(hdevp->meter_clk);
                        clk_rate = clk_get_rate(hdevp->meter_clk);
                }
+               /*for emp data to ddr*/
+               hdevp->axi_clk = clk_get(&pdev->dev, "cts_hdmi_axi_clk");
+               if (IS_ERR(hdevp->axi_clk))
+                       rx_pr("get cts axi clk err\n");
+               else {
+                       clk_set_parent(hdevp->axi_clk, xtal_clk);
+                       clk_set_rate(hdevp->axi_clk, 667000000);
+                       clk_prepare_enable(hdevp->axi_clk);
+                       clk_rate = clk_get_rate(hdevp->axi_clk);
+               }
        } else {
                hdevp->audmeas_clk = clk_get(&pdev->dev, "hdmirx_audmeas_clk");
                if (IS_ERR(hdevp->audmeas_clk))

diff --git a/drivers/amlogic/media/vin/tvin/hdmirx/hdmi_rx_drv.h b/drivers/amlogic/media/vin/tvin/hdmirx/hdmi_rx_drv.h
index 88adf67..522106d 100644 (file)
--- a/drivers/amlogic/media/vin/tvin/hdmirx/hdmi_rx_drv.h
+++ b/drivers/amlogic/media/vin/tvin/hdmirx/hdmi_rx_drv.h
@@ -119,6 +119,7 @@ struct hdmirx_dev_s {
        struct clk *esm_clk;
        struct clk *skp_clk;
        struct clk *meter_clk;
+       struct clk *axi_clk;
        const struct meson_hdmirx_data *data;
 };
 
@@ -264,7 +265,7 @@ struct rx_video_info {
 #define DUMP_MODE_TMDS 1
 #define TMDS_BUFFER_SIZE       0x1e00000 /*30M*/
 #define EMP_BUFFER_SIZE                0x200000        /*2M*/
-#define EMP_BUFF_MAC_PKT_CNT ((EMP_BUFFER_SIZE/2)/32 - 200)
+#define EMP_BUFF_MAX_PKT_CNT ((EMP_BUFFER_SIZE/2)/32 - 200)
 #define TMDS_DATA_BUFFER_SIZE  0x200000
 
 

diff --git a/drivers/amlogic/media/vin/tvin/hdmirx/hdmi_rx_hw.c b/drivers/amlogic/media/vin/tvin/hdmirx/hdmi_rx_hw.c
index 4619b36..507add5 100644 (file)
--- a/drivers/amlogic/media/vin/tvin/hdmirx/hdmi_rx_hw.c
+++ b/drivers/amlogic/media/vin/tvin/hdmirx/hdmi_rx_hw.c
@@ -36,6 +36,9 @@
 #include <linux/io.h>
 #include <linux/amlogic/media/frame_provider/tvin/tvin.h>
 #include <linux/arm-smccc.h>
+#include <linux/slab.h>
+#include <linux/dma-mapping.h>
+#include <linux/highmem.h>
 
 /* Local include */
 #include "hdmi_rx_repeater.h"
@@ -739,7 +742,7 @@ void rx_irq_en(bool enable)
                        data32 |= 1 << 15; /* VSI_RCV */
                        data32 |= 0 << 14; /* AMP_RCV */
                        data32 |= 0 << 13; /* AMP_CHG */
-                       data32 |= 1 << 9; /* EMP_RCV*/
+                       data32 |= 0 << 9; /* EMP_RCV*/
                        data32 |= 0 << 8; /* PD_FIFO_NEW_ENTRY */
                        data32 |= 0 << 4; /* PD_FIFO_OVERFL */
                        data32 |= 0 << 3; /* PD_FIFO_UNDERFL */
@@ -1421,6 +1424,7 @@ void rx_hdcp14_config(const struct hdmi_rx_hdcp *hdcp)
        hdmirx_wr_bits_dwc(DWC_HDCP_CTRL, ENCRIPTION_ENABLE, 1);
 }
 
+#if 0
 void rx_set_term_enable(bool enable)
 {
        if (rx.hdmirxdev->data->chip_id == CHIP_ID_TL1) {
@@ -1429,6 +1433,7 @@ void rx_set_term_enable(bool enable)
                hdmirx_wr_bits_phy(PHY_MAIN_FSM_OVERRIDE1,
                        PHY_TERM_OVERRIDE, enable);
 }
+#endif
 
 void rx_set_term_value(unsigned char port, bool value)
 {
@@ -1736,7 +1741,7 @@ void clk_init(void)
        /* DWC clock enable */
        /* Turn on clk_hdmirx_pclk, also = sysclk */
        wr_reg_hhi(HHI_GCLK_MPEG0,
-       rd_reg_hhi(HHI_GCLK_MPEG0) | (1 << 21));
+               rd_reg_hhi(HHI_GCLK_MPEG0) | (1 << 21));
 
        /* Enable APB3 fail on error */
        /* APB3 to HDMIRX-TOP err_en */
@@ -2135,7 +2140,8 @@ void hdmirx_phy_init(void)
                data32 |= rx.port << 2;
                hdmirx_wr_dwc(DWC_SNPS_PHYG3_CTRL, data32);
 
-               aml_phy_bw_switch(148 * MHz, 0);/*100M,1:10*/
+               aml_phy_bw_switch(rx_get_clock(TOP_HDMI_CABLECLK),
+                       rx_get_scdc_clkrate_sts());/*100M,1:10*/
        } else {
                snps_phyg3_init();
        }
@@ -2940,12 +2946,15 @@ void dump_reg(void)
        }
 
        if (rx.hdmirxdev->data->chip_id == CHIP_ID_TL1) {
-               rx_pr("[0x%-3x]", 0x28);
-               rx_pr("0x%-8x", hdmirx_rd_top(0x28));
-               rx_pr("0x%-8x,0x%-8x,0x%-8x\n",
-                       hdmirx_rd_top(0x29),
-                       hdmirx_rd_top(0x2a),
-                       hdmirx_rd_top(0x2b));
+               for (i = 0x25; i <= 0x84;) {
+                       rx_pr("[0x%-3x]", i);
+                       rx_pr("0x%-8x", hdmirx_rd_top(i));
+                       rx_pr("0x%-8x,0x%-8x,0x%-8x\n",
+                               hdmirx_rd_top(i + 1),
+                               hdmirx_rd_top(i + 2),
+                               hdmirx_rd_top(i + 3));
+                       i = i + 4;
+               }
        }
 
        if (rx.hdmirxdev->data->chip_id < CHIP_ID_TL1) {
@@ -2962,6 +2971,7 @@ void dump_reg(void)
                                hdmirx_rd_phy(i + 3));
                        i = i + 4;
                }
+
        } else if (rx.hdmirxdev->data->chip_id == CHIP_ID_TL1) {
                /* dump phy register */
                rx_pr("\n***AML PHY registers***\n");
@@ -3169,8 +3179,8 @@ void aml_phy_init(unsigned int bw)
 {
        unsigned int data32;
        static unsigned int cnt;
-       unsigned int term_value =
-               hdmirx_rd_top(TOP_HPD_PWR5V);
+       unsigned int term_value = 0x7;/*all terminal on*/
+       /*      hdmirx_rd_top(TOP_HPD_PWR5V);*/
 
        rx_pr("init phy port %d, bw:%d\n", rx.port, bw);
        if (bw == apll_bw_null) {
@@ -3307,8 +3317,8 @@ void aml_phy_init(unsigned int bw)
                data32 |= 0xf << 7;
                wr_reg_hhi(HHI_HDMIRX_PHY_MISC_CNTL0, data32);
                rx_pr("MISC_CNTL0=0x%x\n", data32);
-               wr_reg_hhi(HHI_HDMIRX_PHY_MISC_CNTL1, 0x00000080);
-               wr_reg_hhi(HHI_HDMIRX_PHY_MISC_CNTL2, 0x02218000);
+               wr_reg_hhi(HHI_HDMIRX_PHY_MISC_CNTL1, 0x007f0080);
+               wr_reg_hhi(HHI_HDMIRX_PHY_MISC_CNTL2, 0x02200000);
                /* reset and select data port */
                data32 = 0x00000010;
                data32 |= ((1 << rx.port) << 6);
@@ -3317,15 +3327,14 @@ void aml_phy_init(unsigned int bw)
                data32 |= (1 << 11);
                wr_reg_hhi(HHI_HDMIRX_PHY_MISC_CNTL3, data32);
                udelay(5);
-               wr_reg_hhi(HHI_HDMIRX_PHY_DCHA_CNTL0, 0x00000082);
-               wr_reg_hhi(HHI_HDMIRX_PHY_DCHA_CNTL1, 0x06000000);
-               wr_reg_hhi(HHI_HDMIRX_PHY_DCHA_CNTL2, 0x01004451);
-               wr_reg_hhi(HHI_HDMIRX_PHY_DCHD_CNTL0, 0x006c0041);
-               wr_reg_hhi(HHI_HDMIRX_PHY_DCHD_CNTL1, 0x1e080810);
-               udelay(5);
-               wr_reg_hhi(HHI_HDMIRX_PHY_DCHD_CNTL1, 0x1e480810);
-               udelay(1);
+               wr_reg_hhi(HHI_HDMIRX_PHY_DCHA_CNTL0, 0x351842a2);
+               wr_reg_hhi(HHI_HDMIRX_PHY_DCHA_CNTL1, 0x0700003c);
+               wr_reg_hhi(HHI_HDMIRX_PHY_DCHA_CNTL2, 0x1d00cc31);
+               wr_reg_hhi(HHI_HDMIRX_PHY_DCHD_CNTL0, 0x002c714a);
                wr_reg_hhi(HHI_HDMIRX_PHY_DCHD_CNTL2, 0x00180000);
+               wr_reg_hhi(HHI_HDMIRX_PHY_DCHD_CNTL1, 0x1e062620);
+               udelay(5);
+               wr_reg_hhi(HHI_HDMIRX_PHY_DCHD_CNTL1, 0x1e462620);
        }
        cnt++;
 }
@@ -3502,10 +3511,14 @@ void aml_phy_pw_onoff(unsigned int onoff)
 /*
  * aml phy initial
  */
-void aml_phy_bw_switch(unsigned int cableclk, unsigned int clkrate)
+void aml_phy_bw_switch(unsigned int cableclk_in, unsigned int clkrate)
 {
-       unsigned int bw = aml_check_clk_bandwidth(cableclk, clkrate);
+       unsigned int bw;
+       unsigned int cableclk = cableclk_in;
 
+       if (cableclk == 0)
+               cableclk = 100 * MHz;/*set a default clk*/
+       bw = aml_check_clk_bandwidth(cableclk, clkrate);
        aml_phy_init(bw);
        udelay(1);
        aml_phy_pll_setting(bw, cableclk);
@@ -3581,25 +3594,37 @@ void rx_emp_to_ddr_init(void)
                        rx.empbuff.p_addr_a);
                hdmirx_wr_top(TOP_EMP_DDR_START_B,
                        rx.empbuff.p_addr_b);
-
+               #if 0
+               data  = 0;
+               /*[10: 9] HDMIRX AXI clock mux select: fclk_div3=667MHz*/
+               data |= (2 << 9);
+               /*[    8] HDMIRX AXI clock enable*/
+               data |= (1 << 8);
+               /*[ 6: 0] HDMIRX AXI clock divider: 667/1=667MHz*/
+               data |= (0 << 0);
+               wr_reg_hhi(HHI_HDMIRX_AXI_CLK_CNTL, data);
+               #endif
                /* enable store EMP pkt type */
-               hdmirx_wr_top(TOP_EMP_DDR_FILTER, _BIT(15));
+               data = 0;
+               data |= 0x1 << 15;/* ddr_store_emp */
+               hdmirx_wr_top(TOP_EMP_DDR_FILTER, data);
                /* max pkt count */
-               hdmirx_wr_top(TOP_EMP_CNTMAX, EMP_BUFF_MAC_PKT_CNT);
+               hdmirx_wr_top(TOP_EMP_CNTMAX, EMP_BUFF_MAX_PKT_CNT);
 
                data = 0;
                data |= 0xf << 16;/*[23:16] hs_beat_rate=0xf */
-               /*[14] buffer_info_mode=0 */
+               data |= 0x0 << 14;/*[14] buffer_info_mode=0 */
                data |= 0x1 << 13;/*[13] reset_on_de=1 */
                data |= 0x1 << 12;/*[12] burst_end_on_last_emp=1 */
-               /*[11:2] de_rise_delay=0 */
-               /*[1:0] Endian = 0 */
+               data |= 0x0 << 2;/*[11:2] de_rise_delay=0 */
+               data |= 0x0 << 0;/*[1:0] Endian = 0 */
                hdmirx_wr_top(TOP_EMP_CNTL_0, data);
 
                data = 0;
                data |= 0 << 1;/*ddr_mode[1] 0: emp 1: tmds*/
                hdmirx_wr_top(TOP_EMP_CNTL_1, data);
 
+               data = 0;
                data |= 1;      /*ddr_en[0] 1:enable*/
                hdmirx_wr_top(TOP_EMP_CNTL_1, data);
 
@@ -3607,7 +3632,7 @@ void rx_emp_to_ddr_init(void)
                /* emp field end done at DE rist bit[25]*/
                /* emp last EMP pkt recv done bit[26]*/
                top_intr_maskn_value |= _BIT(25);
-               /*hdmirx_wr_top(TOP_INTR_MASKN, top_intr_maskn_value);*/
+               hdmirx_wr_top(TOP_INTR_MASKN, top_intr_maskn_value);
        }
 
        rx.empbuff.ready = NULL;
@@ -3619,40 +3644,69 @@ void rx_emp_to_ddr_init(void)
 void rx_emp_field_done_irq(void)
 {
        phys_addr_t p_addr;
-       unsigned int recv_pkt_cnt, emp_pkt_cnt;
-       unsigned char *src_addr;
+       unsigned int recv_pkt_cnt, recv_byte_cnt, recv_pagenum;
+       unsigned int emp_pkt_cnt = 0;
+       unsigned char *src_addr = 0;
        unsigned char *dts_addr;
-       unsigned int i, j;
+       unsigned int i, j, k;
        unsigned int datacnt = 0;
+       struct page *cur_start_pg_addr;
 
-       /*emp data start p address*/
+       /*emp data start physical address*/
        p_addr = hdmirx_rd_top(TOP_EMP_DDR_PTR_S_BUF);
+       cur_start_pg_addr = phys_to_page(p_addr);
+
        /*buffer number*/
        recv_pkt_cnt = hdmirx_rd_top(TOP_EMP_RCV_CNT_BUF);
-       /* p addr to v addr for cpu access */
-       src_addr = phys_to_virt(p_addr);
+       recv_byte_cnt = recv_pkt_cnt * 32;
+       recv_pagenum = (recv_byte_cnt >> PAGE_SHIFT) + 1;
 
        if (rx.empbuff.irqcnt & 0x1)
                dts_addr = rx.empbuff.storeB;
        else
                dts_addr = rx.empbuff.storeA;
-       emp_pkt_cnt = 0;
-       if (recv_pkt_cnt < EMP_BUFF_MAC_PKT_CNT) {
-               for (i = 0; i < recv_pkt_cnt; i++) {
-                       /*check PKT_TYPE_EMP = 0x7f*/
-                       if (src_addr[i] == 0x7f) {
-                               emp_pkt_cnt++;
-                               /*32 bytes per emp pkt*/
-                               for (j = 0; j < 32; j++) {
-                                       dts_addr[datacnt] = src_addr[i];
-                                       datacnt++;
+
+       if (recv_pkt_cnt >= EMP_BUFF_MAX_PKT_CNT) {
+               recv_pkt_cnt = EMP_BUFF_MAX_PKT_CNT - 1;
+               rx_pr("pkt cnt err:%d\n", recv_pkt_cnt);
+       }
+
+       for (i = 0; i < recv_pagenum;) {
+               /*one page 4k*/
+               src_addr = kmap_atomic(cur_start_pg_addr + i);
+               if (recv_byte_cnt >= PAGE_SIZE) {
+                       for (j = 0; j < PAGE_SIZE;) {
+                               if (src_addr[j] == 0x7f) {
+                                       emp_pkt_cnt++;
+                                       /*32 bytes per emp pkt*/
+                                       for (k = 0; k < 32; k++) {
+                                               dts_addr[datacnt] =
+                                               src_addr[PAGE_SIZE * i + j + k];
+                                               datacnt++;
+                                       }
                                }
+                               j += 32;
+                       }
+                       recv_byte_cnt -= PAGE_SIZE;
+               } else {
+                       for (j = 0; j < recv_byte_cnt;) {
+                               if (src_addr[j] == 0x7f) {
+                                       emp_pkt_cnt++;
+                                       /*32 bytes per emp pkt*/
+                                       for (k = 0; k < 32; k++) {
+                                               dts_addr[datacnt] =
+                                               src_addr[PAGE_SIZE * i + j + k];
+                                               datacnt++;
+                                       }
+                               }
+                               j += 32;
                        }
-
                }
-       } else {
-               rx_pr("pkt cnt err:%d\n", recv_pkt_cnt);
+               /*release*/
+               __kunmap_atomic(src_addr);
+               i++;
        }
+
        /*ready address*/
        rx.empbuff.ready = dts_addr;
        /*ready pkt cnt*/
@@ -3665,8 +3719,10 @@ void rx_emp_status(void)
 {
        rx_pr("p_addr_a=0x%x\n", rx.empbuff.p_addr_a);
        rx_pr("p_addr_b=0x%x\n", rx.empbuff.p_addr_b);
+       rx_pr("storeA=0x%x\n", (uint32_t)rx.empbuff.storeB);
+       rx_pr("storeB=0x%x\n", (uint32_t)rx.empbuff.storeB);
        rx_pr("irq cnt =0x%x\n", rx.empbuff.irqcnt);
-       rx_pr("p_addr_b=0x%p\n", rx.empbuff.ready);
+       rx_pr("ready=0x%p\n", rx.empbuff.ready);
        rx_pr("dump_mode =0x%x\n", rx.empbuff.dump_mode);
        rx_pr("recv tmp pkt cnt=0x%x\n", rx.empbuff.emppktcnt);
        rx_pr("recv tmds pkt cnt=0x%x\n", rx.empbuff.tmdspktcnt);
@@ -3682,7 +3738,7 @@ void rx_tmds_to_ddr_init(void)
                return;
 
        if (rx.empbuff.pg_addr) {
-               rx_pr("rx_emp_to_ddr_init\n");
+               rx_pr("rx_tmds_to_ddr_init\n");
                /* disable emp rev */
                data = hdmirx_rd_top(TOP_EMP_CNTL_1);
                data &= ~0x1;

diff --git a/drivers/amlogic/media/vin/tvin/hdmirx/hdmi_rx_hw.h b/drivers/amlogic/media/vin/tvin/hdmirx/hdmi_rx_hw.h
index 1934497..e5be681 100644 (file)
--- a/drivers/amlogic/media/vin/tvin/hdmirx/hdmi_rx_hw.h
+++ b/drivers/amlogic/media/vin/tvin/hdmirx/hdmi_rx_hw.h
@@ -629,7 +629,7 @@
 #define PFIFO_GCP_EN           _BIT(17)/*type:0x03*/
 #define PFIFO_ACR_EN           _BIT(16)/*type:0x01*/
 /*tl1*/
-#define PFIFO_EMP_EN           _BIT(9)/*type:0x7f*/
+#define PFIFO_EMP_EN           _BIT(30)/*type:0x7f*/
 
 #define                GCP_GLOBAVMUTE                  _BIT(15)
 /** Packet FIFO clear min/max information */
@@ -1043,6 +1043,9 @@
 #define EXCEPTION_CODE                                 MSK(8, 1)
 #define AUD_PLL_THRESHOLD      1000000
 
+/* tl1 HIU related register */
+#define HHI_HDMIRX_AXI_CLK_CNTL                        (0xb8<<2)
+
 /* tl1 HIU apll register */
 #define HHI_HDMIRX_APLL_CNTL0                  (0xd2<<2)/* 0x4C */
 #define HHI_HDMIRX_APLL_CNTL1                  (0xd3<<2)/* 0x4D */

diff --git a/drivers/amlogic/media/vin/tvin/hdmirx/hdmi_rx_wrapper.c b/drivers/amlogic/media/vin/tvin/hdmirx/hdmi_rx_wrapper.c
index e9a09fd..b55baf7 100644 (file)
--- a/drivers/amlogic/media/vin/tvin/hdmirx/hdmi_rx_wrapper.c
+++ b/drivers/amlogic/media/vin/tvin/hdmirx/hdmi_rx_wrapper.c
@@ -90,6 +90,7 @@ static int err_dbg_cnt;
 static int err_dbg_cnt_max = 500;
 #endif
 int force_vic;
+uint32_t fsm_log_en;
 
 static int aud_sr_stb_max = 20;
 
@@ -343,9 +344,12 @@ static int hdmi_rx_ctrl_irq_handler(void)
                }
        }
 
-       rx_top_intr_stat = hdmirx_rd_top(TOP_INTR_STAT);
-       if (rx_top_intr_stat & _BIT(31))
-               irq_need_clr = 1;
+       if (rx.hdmirxdev->data->chip_id != CHIP_ID_TL1) {
+               rx_top_intr_stat = hdmirx_rd_top(TOP_INTR_STAT);
+               if (rx_top_intr_stat & _BIT(31))
+                       irq_need_clr = 1;
+       }
+
        /* check hdmi open status before dwc isr */
        if (!rx.open_fg) {
                if (irq_need_clr)
@@ -531,7 +535,13 @@ reisr:hdmirx_top_intr_stat = hdmirx_rd_top(TOP_INTR_STAT);
                rx_pr("[isr] enc fall\n");
 
        /* must clear ip interrupt quickly */
-       if (hdmirx_top_intr_stat & (~(1 << 30))) {
+       if (rx.hdmirxdev->data->chip_id == CHIP_ID_TL1) {
+               hdmirx_top_intr_stat &= 0x1;
+       } else {
+               hdmirx_top_intr_stat &= (~(1 << 30));
+       }
+
+       if (hdmirx_top_intr_stat) {
                error = hdmi_rx_ctrl_irq_handler();
                if (error < 0) {
                        if (error != -EPERM) {
@@ -541,8 +551,11 @@ reisr:hdmirx_top_intr_stat = hdmirx_rd_top(TOP_INTR_STAT);
                        }
                }
        }
-       if (error == 1)
-               goto reisr;
+
+       if (rx.hdmirxdev->data->chip_id != CHIP_ID_TL1) {
+               if (error == 1)
+                       goto reisr;
+       }
        /* check the ip interrupt again */
        /*hdmirx_top_intr_stat = hdmirx_rd_top(TOP_INTR_STAT);
         *if (hdmirx_top_intr_stat & (1 << 31)) {
@@ -1371,6 +1384,9 @@ void fsm_restart(void)
        vic_check_en = true;
        dvi_check_en = true;
        rx.state = FSM_INIT;
+       rx.physts.cable_clk = 0;
+       rx.physts.pll_rate = 0;
+       rx.physts.phy_bw = 0;
        rx_pr("force_fsm_init\n");
 }
 
@@ -1728,6 +1744,9 @@ int rx_set_global_variable(const char *buf, int size)
                return pr_var(ignore_sscp_charerr, index);
        if (set_pr_var(tmpbuf, ignore_sscp_tmds, value, &index, ret))
                return pr_var(ignore_sscp_tmds, index);
+       if (set_pr_var(tmpbuf, fsm_log_en, value, &index, ret))
+               return pr_var(fsm_log_en, index);
+
        return 0;
 }
 
@@ -1832,6 +1851,7 @@ void rx_get_global_variable(const char *buf)
        pr_var(esd_phy_rst_max, i++);
        pr_var(ignore_sscp_charerr, i++);
        pr_var(ignore_sscp_tmds, i++);
+       pr_var(fsm_log_en, i++);
 }
 
 void skip_frame(unsigned int cnt)
@@ -2004,17 +2024,14 @@ void rx_clk_rate_monitor(void)
 
        cur_clk_rate = rx_get_scdc_clkrate_sts();
        cur_phy_bw = aml_check_clk_bandwidth(cur_cable_clk, cur_clk_rate);
-
-       if ((rx.cur_5v_sts) && (cur_cable_clk > ((20 * MHz))) &&
-               ((rx.physts.phy_bw != cur_phy_bw) ||
+       if ((rx.cur_5v_sts) &&  ((rx.physts.phy_bw != cur_phy_bw) ||
                        (rx.physts.clk_rate != cur_clk_rate) ||
                        (clk_diff > (1000 * KHz)))) {
-
                if (phy_bw_cnt++ > 1) {
                        phy_bw_cnt = 0;
                        while (i++ < 3) {
-                               rx_pr("chg phy i=%d, cable clk:%d\n",
-                                       i, cur_cable_clk);
+                               rx_pr("chg phy i=%d, cabclk:%d, clkrate:%d\n",
+                                       i, cur_cable_clk, cur_clk_rate);
                                aml_phy_bw_switch(cur_cable_clk, cur_clk_rate);
                                if ((cur_cable_clk < (20 * MHz)) ||
                                        aml_phy_pll_lock())
@@ -2119,6 +2136,21 @@ void rx_err_monitor(void)
        }
 }
 
+char *fsm_st[] = {
+       "FSM_5V_LOST",
+       "FSM_INIT",
+       "FSM_HPD_LOW",
+       "FSM_HPD_HIGH",
+       "FSM_WAIT_CLK_STABLE",
+       "FSM_EQ_START",
+       "FSM_WAIT_EQ_DONE",
+       "FSM_SIG_UNSTABLE",
+       "FSM_SIG_WAIT_STABLE",
+       "FSM_SIG_STABLE",
+       "FSM_SIG_READY",
+       "FSM_NULL",
+};
+
 /*
  * FUNC: rx_main_state_machine
  * signal detection main process
@@ -2403,7 +2435,7 @@ void rx_main_state_machine(void)
                                if (aud_sts == E_REQUESTCLK_ERR) {
                                        hdmirx_phy_init();
                                        rx.state = FSM_WAIT_CLK_STABLE;
-                                       rx.pre_state = FSM_SIG_READY;
+                                       /*rx.pre_state = FSM_SIG_READY;*/
                                        rx_pr("reqclk err->wait_clk\n");
                                } else if (aud_sts == E_PLLRATE_CHG)
                                        rx_aud_pll_ctl(1);
@@ -2426,6 +2458,13 @@ void rx_main_state_machine(void)
        default:
                break;
        }
+
+       /* for fsm debug */
+       if (fsm_log_en && (rx.state != rx.pre_state)) {
+               rx_pr("fsm state:%d(%s) to %d(%s)\n", rx.pre_state,
+                       fsm_st[rx.pre_state], rx.state, fsm_st[rx.state]);
+               rx.pre_state = rx.state;
+       }
 }
  #else
 void rx_main_state_machine(void)