drm/sun4i: Fix polarity configuration for DW HDMI PHY

Current polarity configuration code is cleary wrong since it compares
same flag two times. However, even if flag name is fixed, it won't work
well for resolutions which have one polarity positive and another
negative.

Fix that by properly set each bit according to each polarity. Since
those two bits are not described in any documentation, relationships
were obtained by experimentation.

Fixes: b7c7436a5ff0 ("drm/sun4i: Implement A83T HDMI driver")

Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20180301213442.16677-10-jernej.skrabec@siol.net

diff --git a/drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c b/drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c
index e5bfcdd..9d2f11c 100644 (file)
--- a/drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c
+++ b/drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c
@@ -10,7 +10,8 @@
 #define SUN8I_HDMI_PHY_DBG_CTRL_REG    0x0000
 #define SUN8I_HDMI_PHY_DBG_CTRL_PX_LOCK                BIT(0)
 #define SUN8I_HDMI_PHY_DBG_CTRL_POL_MASK       GENMASK(15, 8)
-#define SUN8I_HDMI_PHY_DBG_CTRL_POL(val)       (val << 8)
+#define SUN8I_HDMI_PHY_DBG_CTRL_POL_NHSYNC     BIT(8)
+#define SUN8I_HDMI_PHY_DBG_CTRL_POL_NVSYNC     BIT(9)
 #define SUN8I_HDMI_PHY_DBG_CTRL_ADDR_MASK      GENMASK(23, 16)
 #define SUN8I_HDMI_PHY_DBG_CTRL_ADDR(addr)     (addr << 16)
 
@@ -35,14 +36,14 @@ static int sun8i_hdmi_phy_config(struct dw_hdmi *hdmi, void *data,
        struct sun8i_hdmi_phy *phy = (struct sun8i_hdmi_phy *)data;
        u32 val = 0;
 
-       if ((mode->flags & DRM_MODE_FLAG_NHSYNC) &&
-           (mode->flags & DRM_MODE_FLAG_NHSYNC)) {
-               val = 0x03;
-       }
+       if (mode->flags & DRM_MODE_FLAG_NHSYNC)
+               val |= SUN8I_HDMI_PHY_DBG_CTRL_POL_NHSYNC;
+
+       if (mode->flags & DRM_MODE_FLAG_NVSYNC)
+               val |= SUN8I_HDMI_PHY_DBG_CTRL_POL_NVSYNC;
 
        regmap_update_bits(phy->regs, SUN8I_HDMI_PHY_DBG_CTRL_REG,
-                          SUN8I_HDMI_PHY_DBG_CTRL_POL_MASK,
-                          SUN8I_HDMI_PHY_DBG_CTRL_POL(val));
+                          SUN8I_HDMI_PHY_DBG_CTRL_POL_MASK, val);
 
        regmap_update_bits(phy->regs, SUN8I_HDMI_PHY_REXT_CTRL_REG,
                           SUN8I_HDMI_PHY_REXT_CTRL_REXT_EN,