return true;
case CONST_DOUBLE:
- if (GET_MODE (x) == VOIDmode)
+ if (GET_MODE (x) == VOIDmode || GET_MODE (x) == SFmode
+ || GET_MODE (x) == DFmode)
return true;
return satisfies_constraint_G (x);
e Print 64 - constant, for DImode rotates.
F A floating point constant 0.0 emitted as f0, or 1.0 emitted as f1, or
a floating point register emitted normally.
+ G A floating point constant.
I Invert a predicate register by adding 1.
J Select the proper predicate register for a condition.
j Select the inverse predicate register for a condition.
fputs (str, file);
return;
+ case 'G':
+ {
+ long val[4];
+ REAL_VALUE_TYPE rv;
+ REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
+ real_to_target (val, &rv, GET_MODE (x));
+ if (GET_MODE (x) == SFmode)
+ fprintf (file, "0x%08lx", val[0] & 0xffffffff);
+ else if (GET_MODE (x) == DFmode)
+ fprintf (file, "0x%08lx%08lx", (WORDS_BIG_ENDIAN ? val[0] : val[1])
+ & 0xffffffff,
+ (WORDS_BIG_ENDIAN ? val[1] : val[0])
+ & 0xffffffff);
+ else
+ output_operand_lossage ("invalid %%G mode");
+ }
+ return;
+
case 'I':
fputs (reg_names [REGNO (x) + 1], file);
return;
})
(define_insn "movsf_internal"
- [(set (match_operand:SF 0 "destination_operand" "=f,f, Q,*r, f,*r,*r, m")
- (match_operand:SF 1 "general_operand" "fG,Q,fG,fG,*r,*r, m,*r"))]
+ [(set (match_operand:SF 0 "destination_operand" "=f,f, Q,*r, f,*r,*r, m,*r")
+ (match_operand:SF 1 "general_operand" "fG,Q,fG,fG,*r,*r, m,*r, F"))]
"ia64_move_ok (operands[0], operands[1])"
"@
mov %0 = %F1
setf.s %0 = %1
mov %0 = %1
ld4%O1 %0 = %1%P1
- st4%Q0 %0 = %1%P0"
- [(set_attr "itanium_class" "fmisc,fld,stf,frfr,tofr,ialu,ld,st")
+ st4%Q0 %0 = %1%P0
+ movl %0 = %G1"
+ [(set_attr "itanium_class" "fmisc,fld,stf,frfr,tofr,ialu,ld,st,long_i")
(set_attr "speculable1" "yes")
- (set_attr "speculable2" "no, yes,no, no, no, no, yes,no")])
+ (set_attr "speculable2" "no, yes,no, no, no, no, yes,no,no")])
(define_expand "movdf"
[(set (match_operand:DF 0 "general_operand" "")
})
(define_insn "movdf_internal"
- [(set (match_operand:DF 0 "destination_operand" "=f,f, Q,*r, f,*r,*r, m")
- (match_operand:DF 1 "general_operand" "fG,Q,fG,fG,*r,*r, m,*r"))]
+ [(set (match_operand:DF 0 "destination_operand" "=f,f, Q,*r, f,*r,*r, m,*r")
+ (match_operand:DF 1 "general_operand" "fG,Q,fG,fG,*r,*r, m,*r, F"))]
"ia64_move_ok (operands[0], operands[1])"
"@
mov %0 = %F1
setf.d %0 = %1
mov %0 = %1
ld8%O1 %0 = %1%P1
- st8%Q0 %0 = %1%P0"
- [(set_attr "itanium_class" "fmisc,fld,stf,frfr,tofr,ialu,ld,st")
+ st8%Q0 %0 = %1%P0
+ movl %0 = %G1"
+ [(set_attr "itanium_class" "fmisc,fld,stf,frfr,tofr,ialu,ld,st,long_i")
(set_attr "speculable1" "yes")
- (set_attr "speculable2" "no, yes,no, no, no, no, yes,no")])
+ (set_attr "speculable2" "no, yes,no, no, no, no, yes,no,no")])
;; With no offsettable memory references, we've got to have a scratch
;; around to play with the second word if the variable winds up in GRs.