; operation into two DImode ADDs.
(define_insn "<ti*>add<mode>3"
[(set (match_operand:VIT 0 "nonimmediate_operand" "=v")
- (plus:VIT (match_operand:VIT 1 "nonimmediate_operand" "v")
- (match_operand:VIT 2 "general_operand" "v")))]
+ (plus:VIT (match_operand:VIT 1 "nonimmediate_operand" "%v")
+ (match_operand:VIT 2 "general_operand" "v")))]
"TARGET_VX"
"va<bhfgq>\t%v0,%v1,%v2"
[(set_attr "op_type" "VRR")])
; vmlb, vmlhw, vmlf
(define_insn "mul<mode>3"
[(set (match_operand:VI_QHS 0 "register_operand" "=v")
- (mult:VI_QHS (match_operand:VI_QHS 1 "register_operand" "v")
+ (mult:VI_QHS (match_operand:VI_QHS 1 "register_operand" "%v")
(match_operand:VI_QHS 2 "register_operand" "v")))]
"TARGET_VX"
"vml<bhfgq><w>\t%v0,%v1,%v2"
(define_insn "and<mode>3"
[(set (match_operand:VT 0 "register_operand" "=v")
- (and:VT (match_operand:VT 1 "register_operand" "v")
+ (and:VT (match_operand:VT 1 "register_operand" "%v")
(match_operand:VT 2 "register_operand" "v")))]
"TARGET_VX"
"vn\t%v0,%v1,%v2"
(define_insn "ior<mode>3"
[(set (match_operand:VT 0 "register_operand" "=v")
- (ior:VT (match_operand:VT 1 "register_operand" "v")
+ (ior:VT (match_operand:VT 1 "register_operand" "%v")
(match_operand:VT 2 "register_operand" "v")))]
"TARGET_VX"
"vo\t%v0,%v1,%v2"
(define_insn "xor<mode>3"
[(set (match_operand:VT 0 "register_operand" "=v")
- (xor:VT (match_operand:VT 1 "register_operand" "v")
+ (xor:VT (match_operand:VT 1 "register_operand" "%v")
(match_operand:VT 2 "register_operand" "v")))]
"TARGET_VX"
"vx\t%v0,%v1,%v2"
; vmnb, vmnh, vmnf, vmng
(define_insn "smin<mode>3"
[(set (match_operand:VI 0 "register_operand" "=v")
- (smin:VI (match_operand:VI 1 "register_operand" "v")
+ (smin:VI (match_operand:VI 1 "register_operand" "%v")
(match_operand:VI 2 "register_operand" "v")))]
"TARGET_VX"
"vmn<bhfgq>\t%v0,%v1,%v2"
; vmxb, vmxh, vmxf, vmxg
(define_insn "smax<mode>3"
[(set (match_operand:VI 0 "register_operand" "=v")
- (smax:VI (match_operand:VI 1 "register_operand" "v")
+ (smax:VI (match_operand:VI 1 "register_operand" "%v")
(match_operand:VI 2 "register_operand" "v")))]
"TARGET_VX"
"vmx<bhfgq>\t%v0,%v1,%v2"
; vmnlb, vmnlh, vmnlf, vmnlg
(define_insn "umin<mode>3"
[(set (match_operand:VI 0 "register_operand" "=v")
- (umin:VI (match_operand:VI 1 "register_operand" "v")
+ (umin:VI (match_operand:VI 1 "register_operand" "%v")
(match_operand:VI 2 "register_operand" "v")))]
"TARGET_VX"
"vmnl<bhfgq>\t%v0,%v1,%v2"
; vmxlb, vmxlh, vmxlf, vmxlg
(define_insn "umax<mode>3"
[(set (match_operand:VI 0 "register_operand" "=v")
- (umax:VI (match_operand:VI 1 "register_operand" "v")
+ (umax:VI (match_operand:VI 1 "register_operand" "%v")
(match_operand:VI 2 "register_operand" "v")))]
"TARGET_VX"
"vmxl<bhfgq>\t%v0,%v1,%v2"
; vmeb, vmeh, vmef
(define_insn "vec_widen_smult_even_<mode>"
- [(set (match_operand:<vec_double> 0 "register_operand" "=v")
- (unspec:<vec_double> [(match_operand:VI_QHS 1 "register_operand" "v")
+ [(set (match_operand:<vec_double> 0 "register_operand" "=v")
+ (unspec:<vec_double> [(match_operand:VI_QHS 1 "register_operand" "%v")
(match_operand:VI_QHS 2 "register_operand" "v")]
UNSPEC_VEC_SMULT_EVEN))]
"TARGET_VX"
; vmleb, vmleh, vmlef
(define_insn "vec_widen_umult_even_<mode>"
[(set (match_operand:<vec_double> 0 "register_operand" "=v")
- (unspec:<vec_double> [(match_operand:VI_QHS 1 "register_operand" "v")
+ (unspec:<vec_double> [(match_operand:VI_QHS 1 "register_operand" "%v")
(match_operand:VI_QHS 2 "register_operand" "v")]
UNSPEC_VEC_UMULT_EVEN))]
"TARGET_VX"
; vmob, vmoh, vmof
(define_insn "vec_widen_smult_odd_<mode>"
[(set (match_operand:<vec_double> 0 "register_operand" "=v")
- (unspec:<vec_double> [(match_operand:VI_QHS 1 "register_operand" "v")
+ (unspec:<vec_double> [(match_operand:VI_QHS 1 "register_operand" "%v")
(match_operand:VI_QHS 2 "register_operand" "v")]
UNSPEC_VEC_SMULT_ODD))]
"TARGET_VX"
; vmlob, vmloh, vmlof
(define_insn "vec_widen_umult_odd_<mode>"
[(set (match_operand:<vec_double> 0 "register_operand" "=v")
- (unspec:<vec_double> [(match_operand:VI_QHS 1 "register_operand" "v")
+ (unspec:<vec_double> [(match_operand:VI_QHS 1 "register_operand" "%v")
(match_operand:VI_QHS 2 "register_operand" "v")]
UNSPEC_VEC_UMULT_ODD))]
"TARGET_VX"
(define_insn "addv2df3"
[(set (match_operand:V2DF 0 "register_operand" "=v")
- (plus:V2DF (match_operand:V2DF 1 "register_operand" "v")
+ (plus:V2DF (match_operand:V2DF 1 "register_operand" "%v")
(match_operand:V2DF 2 "register_operand" "v")))]
"TARGET_VX"
"vfadb\t%v0,%v1,%v2"
(define_insn "subv2df3"
[(set (match_operand:V2DF 0 "register_operand" "=v")
- (minus:V2DF (match_operand:V2DF 1 "register_operand" "v")
+ (minus:V2DF (match_operand:V2DF 1 "register_operand" "%v")
(match_operand:V2DF 2 "register_operand" "v")))]
"TARGET_VX"
"vfsdb\t%v0,%v1,%v2"
(define_insn "mulv2df3"
[(set (match_operand:V2DF 0 "register_operand" "=v")
- (mult:V2DF (match_operand:V2DF 1 "register_operand" "v")
+ (mult:V2DF (match_operand:V2DF 1 "register_operand" "%v")
(match_operand:V2DF 2 "register_operand" "v")))]
"TARGET_VX"
"vfmdb\t%v0,%v1,%v2"
(define_insn "fmav2df4"
[(set (match_operand:V2DF 0 "register_operand" "=v")
- (fma:V2DF (match_operand:V2DF 1 "register_operand" "v")
+ (fma:V2DF (match_operand:V2DF 1 "register_operand" "%v")
(match_operand:V2DF 2 "register_operand" "v")
(match_operand:V2DF 3 "register_operand" "v")))]
"TARGET_VX"
(define_insn "fmsv2df4"
[(set (match_operand:V2DF 0 "register_operand" "=v")
- (fma:V2DF (match_operand:V2DF 1 "register_operand" "v")
+ (fma:V2DF (match_operand:V2DF 1 "register_operand" "%v")
(match_operand:V2DF 2 "register_operand" "v")
(neg:V2DF (match_operand:V2DF 3 "register_operand" "v"))))]
"TARGET_VX"
; Emulate with compare + select
(define_insn_and_split "smaxv2df3"
[(set (match_operand:V2DF 0 "register_operand" "=v")
- (smax:V2DF (match_operand:V2DF 1 "register_operand" "v")
+ (smax:V2DF (match_operand:V2DF 1 "register_operand" "%v")
(match_operand:V2DF 2 "register_operand" "v")))]
"TARGET_VX"
"#"
; Emulate with compare + select
(define_insn_and_split "sminv2df3"
[(set (match_operand:V2DF 0 "register_operand" "=v")
- (smin:V2DF (match_operand:V2DF 1 "register_operand" "v")
+ (smin:V2DF (match_operand:V2DF 1 "register_operand" "%v")
(match_operand:V2DF 2 "register_operand" "v")))]
"TARGET_VX"
"#"
(define_insn "vec_addc<mode>"
[(set (match_operand:VI_HW 0 "register_operand" "=v")
- (unspec:VI_HW [(match_operand:VI_HW 1 "register_operand" "v")
+ (unspec:VI_HW [(match_operand:VI_HW 1 "register_operand" "%v")
(match_operand:VI_HW 2 "register_operand" "v")]
UNSPEC_VEC_ADDC))]
"TARGET_VX"
(define_insn "vec_addc_u128"
[(set (match_operand:V16QI 0 "register_operand" "=v")
- (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
+ (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "%v")
(match_operand:V16QI 2 "register_operand" "v")]
UNSPEC_VEC_ADDC_U128))]
"TARGET_VX"
(define_insn "vec_adde_u128"
[(set (match_operand:V16QI 0 "register_operand" "=v")
- (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
+ (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "%v")
(match_operand:V16QI 2 "register_operand" "v")
(match_operand:V16QI 3 "register_operand" "v")]
UNSPEC_VEC_ADDE_U128))]
(define_insn "vec_addec_u128"
[(set (match_operand:V16QI 0 "register_operand" "=v")
- (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
+ (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "%v")
(match_operand:V16QI 2 "register_operand" "v")
(match_operand:V16QI 3 "register_operand" "v")]
UNSPEC_VEC_ADDEC_U128))]
(define_insn "vec_avg<mode>"
[(set (match_operand:VI_HW 0 "register_operand" "=v")
- (unspec:VI_HW [(match_operand:VI_HW 1 "register_operand" "v")
+ (unspec:VI_HW [(match_operand:VI_HW 1 "register_operand" "%v")
(match_operand:VI_HW 2 "register_operand" "v")]
UNSPEC_VEC_AVG))]
"TARGET_VX"
(define_insn "vec_avgu<mode>"
[(set (match_operand:VI_HW 0 "register_operand" "=v")
- (unspec:VI_HW [(match_operand:VI_HW 1 "register_operand" "v")
+ (unspec:VI_HW [(match_operand:VI_HW 1 "register_operand" "%v")
(match_operand:VI_HW 2 "register_operand" "v")]
UNSPEC_VEC_AVGU))]
"TARGET_VX"
; vmalb, vmalh, vmalf, vmalg
(define_insn "vec_vmal<mode>"
[(set (match_operand:VI_HW_QHS 0 "register_operand" "=v")
- (unspec:VI_HW_QHS [(match_operand:VI_HW_QHS 1 "register_operand" "v")
- (match_operand:VI_HW_QHS 2 "register_operand" "v")
- (match_operand:VI_HW_QHS 3 "register_operand" "v")]
+ (unspec:VI_HW_QHS [(match_operand:VI_HW_QHS 1 "register_operand" "%v")
+ (match_operand:VI_HW_QHS 2 "register_operand" "v")
+ (match_operand:VI_HW_QHS 3 "register_operand" "v")]
UNSPEC_VEC_VMAL))]
"TARGET_VX"
"vmal<bhfgq><w>\t%v0,%v1,%v2,%v3"
; vmahb; vmahh, vmahf, vmahg
(define_insn "vec_vmah<mode>"
[(set (match_operand:VI_HW_QHS 0 "register_operand" "=v")
- (unspec:VI_HW_QHS [(match_operand:VI_HW_QHS 1 "register_operand" "v")
- (match_operand:VI_HW_QHS 2 "register_operand" "v")
- (match_operand:VI_HW_QHS 3 "register_operand" "v")]
+ (unspec:VI_HW_QHS [(match_operand:VI_HW_QHS 1 "register_operand" "%v")
+ (match_operand:VI_HW_QHS 2 "register_operand" "v")
+ (match_operand:VI_HW_QHS 3 "register_operand" "v")]
UNSPEC_VEC_VMAH))]
"TARGET_VX"
"vmah<bhfgq>\t%v0,%v1,%v2,%v3"
; vmalhb; vmalhh, vmalhf, vmalhg
(define_insn "vec_vmalh<mode>"
[(set (match_operand:VI_HW_QHS 0 "register_operand" "=v")
- (unspec:VI_HW_QHS [(match_operand:VI_HW_QHS 1 "register_operand" "v")
- (match_operand:VI_HW_QHS 2 "register_operand" "v")
- (match_operand:VI_HW_QHS 3 "register_operand" "v")]
+ (unspec:VI_HW_QHS [(match_operand:VI_HW_QHS 1 "register_operand" "%v")
+ (match_operand:VI_HW_QHS 2 "register_operand" "v")
+ (match_operand:VI_HW_QHS 3 "register_operand" "v")]
UNSPEC_VEC_VMALH))]
"TARGET_VX"
"vmalh<bhfgq>\t%v0,%v1,%v2,%v3"
; vmaeb; vmaeh, vmaef, vmaeg
(define_insn "vec_vmae<mode>"
[(set (match_operand:<vec_double> 0 "register_operand" "=v")
- (unspec:<vec_double> [(match_operand:VI_HW_QHS 1 "register_operand" "v")
- (match_operand:VI_HW_QHS 2 "register_operand" "v")
+ (unspec:<vec_double> [(match_operand:VI_HW_QHS 1 "register_operand" "%v")
+ (match_operand:VI_HW_QHS 2 "register_operand" "v")
(match_operand:<vec_double> 3 "register_operand" "v")]
UNSPEC_VEC_VMAE))]
"TARGET_VX"
; vmaleb; vmaleh, vmalef, vmaleg
(define_insn "vec_vmale<mode>"
[(set (match_operand:<vec_double> 0 "register_operand" "=v")
- (unspec:<vec_double> [(match_operand:VI_HW_QHS 1 "register_operand" "v")
+ (unspec:<vec_double> [(match_operand:VI_HW_QHS 1 "register_operand" "%v")
(match_operand:VI_HW_QHS 2 "register_operand" "v")
(match_operand:<vec_double> 3 "register_operand" "v")]
UNSPEC_VEC_VMALE))]
; vmaob; vmaoh, vmaof, vmaog
(define_insn "vec_vmao<mode>"
[(set (match_operand:<vec_double> 0 "register_operand" "=v")
- (unspec:<vec_double> [(match_operand:VI_HW_QHS 1 "register_operand" "v")
+ (unspec:<vec_double> [(match_operand:VI_HW_QHS 1 "register_operand" "%v")
(match_operand:VI_HW_QHS 2 "register_operand" "v")
(match_operand:<vec_double> 3 "register_operand" "v")]
UNSPEC_VEC_VMAO))]
; vmhb, vmhh, vmhf
(define_insn "vec_smulh<mode>"
[(set (match_operand:VI_HW_QHS 0 "register_operand" "=v")
- (unspec:VI_HW_QHS [(match_operand:VI_HW_QHS 1 "register_operand" "v")
+ (unspec:VI_HW_QHS [(match_operand:VI_HW_QHS 1 "register_operand" "%v")
(match_operand:VI_HW_QHS 2 "register_operand" "v")]
UNSPEC_VEC_SMULT_HI))]
"TARGET_VX"
; vmlhb, vmlhh, vmlhf
(define_insn "vec_umulh<mode>"
[(set (match_operand:VI_HW_QHS 0 "register_operand" "=v")
- (unspec:VI_HW_QHS [(match_operand:VI_HW_QHS 1 "register_operand" "v")
+ (unspec:VI_HW_QHS [(match_operand:VI_HW_QHS 1 "register_operand" "%v")
(match_operand:VI_HW_QHS 2 "register_operand" "v")]
UNSPEC_VEC_UMULT_HI))]
"TARGET_VX"
(define_insn "vec_nor<mode>3"
[(set (match_operand:VT_HW 0 "register_operand" "=v")
- (not:VT_HW (ior:VT_HW (match_operand:VT_HW 1 "register_operand" "v")
+ (not:VT_HW (ior:VT_HW (match_operand:VT_HW 1 "register_operand" "%v")
(match_operand:VT_HW 2 "register_operand" "v"))))]
"TARGET_VX"
"vno\t%v0,%v1,%v2"