clk: uniphier: add audio system clock

Add clock for audio subsystem (AIO) and SoC internal audio codec
(EVEA) on UniPhier LD11/LD20 SoCs.

Signed-off-by: Katsuhiro Suzuki <suzuki.katsuhiro@socionext.com>
Acked-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>

diff --git a/drivers/clk/uniphier/clk-uniphier-sys.c b/drivers/clk/uniphier/clk-uniphier-sys.c
index 4422570..5204869 100644 (file)
--- a/drivers/clk/uniphier/clk-uniphier-sys.c
+++ b/drivers/clk/uniphier/clk-uniphier-sys.c
@@ -57,6 +57,14 @@
 #define UNIPHIER_PRO4_SYS_CLK_USB3(idx, ch)                            \
        UNIPHIER_CLK_GATE("usb3" #ch, (idx), NULL, 0x2104, 16 + (ch))
 
+#define UNIPHIER_LD11_SYS_CLK_AIO(idx)                                 \
+       UNIPHIER_CLK_FACTOR("aio-io200m", -1, "spll", 1, 10),           \
+       UNIPHIER_CLK_GATE("aio", (idx), "aio-io200m", 0x2108, 0)
+
+#define UNIPHIER_LD11_SYS_CLK_EVEA(idx)                                        \
+       UNIPHIER_CLK_FACTOR("evea-io100m", -1, "spll", 1, 20),          \
+       UNIPHIER_CLK_GATE("evea", (idx), "evea-io100m", 0x2108, 1)
+
 #define UNIPHIER_PRO4_SYS_CLK_ETHER(idx)                               \
        UNIPHIER_CLK_GATE("ether", (idx), NULL, 0x2104, 12)
 
@@ -153,6 +161,8 @@ const struct uniphier_clk_data uniphier_ld11_sys_clk_data[] = {
        UNIPHIER_LD11_SYS_CLK_ETHER(6),
        UNIPHIER_LD11_SYS_CLK_STDMAC(8),                        /* HSC, MIO */
        UNIPHIER_CLK_FACTOR("usb2", -1, "ref", 24, 25),
+       UNIPHIER_LD11_SYS_CLK_AIO(40),
+       UNIPHIER_LD11_SYS_CLK_EVEA(41),
        /* CPU gears */
        UNIPHIER_CLK_DIV4("cpll", 2, 3, 4, 8),
        UNIPHIER_CLK_DIV4("mpll", 2, 3, 4, 8),
@@ -190,6 +200,8 @@ const struct uniphier_clk_data uniphier_ld20_sys_clk_data[] = {
        UNIPHIER_CLK_GATE("usb30", 14, NULL, 0x210c, 14),
        UNIPHIER_CLK_GATE("usb30-phy0", 16, NULL, 0x210c, 12),
        UNIPHIER_CLK_GATE("usb30-phy1", 17, NULL, 0x210c, 13),
+       UNIPHIER_LD11_SYS_CLK_AIO(40),
+       UNIPHIER_LD11_SYS_CLK_EVEA(41),
        /* CPU gears */
        UNIPHIER_CLK_DIV4("cpll", 2, 3, 4, 8),
        UNIPHIER_CLK_DIV4("spll", 2, 3, 4, 8),