AMDGPU/GlobalISel: Define instruction mapping for G_FCONSTANT

Patch by Tom Stellard

llvm-svn: 326468

diff --git a/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp b/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
index 811242c29e01d934cd9593fbd83f48d1c393114f..4454e5056e3cf4ad52f5437a23ee448ee64a9f76 100644 (file)
--- a/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
@@ -174,6 +174,7 @@ AMDGPURegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
   default:
     IsComplete = false;
     break;
+  case AMDGPU::G_FCONSTANT:
   case AMDGPU::G_CONSTANT: {
     unsigned Size = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits();
     OpdsMapping[0] = AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, Size);

diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-default.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-default.mir
new file mode 100644 (file)
index 0000000..d0499e0
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-default.mir
@@ -0,0 +1,31 @@
+# RUN: llc -O0 -march amdgcn -mcpu=fiji -run-pass=regbankselect -global-isel %s -o - | FileCheck %s
+
+# Check the default mappings for various instructions.
+
+---
+# CHECK-LABEL: name: test_fconstant_f32_1
+name:            test_fconstant_f32_1
+legalized:       true
+body: |
+  bb.0:
+    ; CHECK: %0:sgpr(s32) = G_FCONSTANT float 1.0
+    %0:_(s32) = G_FCONSTANT float 1.0
+...
+---
+# CHECK-LABEL: name: test_fconstant_f64_1
+name:            test_fconstant_f64_1
+legalized:       true
+body: |
+  bb.0:
+    ; CHECK: %0:sgpr(s64) = G_FCONSTANT double 1.0
+    %0:_(s64) = G_FCONSTANT double 1.0
+...
+---
+# CHECK-LABEL: name: test_fconstant_f16_1
+name:            test_fconstant_f16_1
+legalized:       true
+body: |
+  bb.0:
+    ; CHECK: %0:sgpr(s32) = G_FCONSTANT half 0xH3C00
+    %0:_(s32) = G_FCONSTANT half 1.0
+...