[Hexagon] Add LLVM codegen testcases for V6_[add|sub]carryo intrinsics

diff --git a/llvm/test/CodeGen/Hexagon/hvx-dbl-dual-output.ll b/llvm/test/CodeGen/Hexagon/hvx-dbl-dual-output.ll
index b047e38..6127473 100644 (file)
--- a/llvm/test/CodeGen/Hexagon/hvx-dbl-dual-output.ll
+++ b/llvm/test/CodeGen/Hexagon/hvx-dbl-dual-output.ll
@@ -1,39 +1,84 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -march=hexagon < %s | FileCheck %s
 
 ; Test that we compile the HVX dual output intrinsics.
 
+define inreg <32 x i32> @f0(<32 x i32> %a0, <32 x i32> %a1, <32 x i32>* %a2) #0 {
 ; CHECK-LABEL: f0:
-; CHECK: v{{[0-9]+}}.w = vadd(v{{[0-9]+}}.w,v{{[0-9]+}}.w,q{{[0-3]}}):carry
-define inreg <32 x i32> @f0(<32 x i32> %a0, <32 x i32> %a1, i8* nocapture readonly %a2) #0 {
+; CHECK:       // %bb.0: // %b0
+; CHECK-NEXT:    {
+; CHECK-NEXT:     r1 = #-1
+; CHECK-NEXT:     v2 = vmem(r0+#0)
+; CHECK-NEXT:    }
+; CHECK-NEXT:    {
+; CHECK-NEXT:     q0 = vand(v2,r1)
+; CHECK-NEXT:    }
+; CHECK-NEXT:    {
+; CHECK-NEXT:     v0.w = vadd(v0.w,v1.w,q0):carry
+; CHECK-NEXT:     jumpr r31
+; CHECK-NEXT:    }
 b0:
-  %v0 = bitcast i8* %a2 to <32 x i32>*
-  %v1 = load <32 x i32>, <32 x i32>* %v0, align 128
-  %v2 = tail call <128 x i1> @llvm.hexagon.V6.vandvrt.128B(<32 x i32> %v1, i32 -1)
-  %v3 = tail call { <32 x i32>, <128 x i1> } @llvm.hexagon.V6.vaddcarry.128B(<32 x i32> %a0, <32 x i32> %a1, <128 x i1> %v2)
-  %v4 = extractvalue { <32 x i32>, <128 x i1> } %v3, 0
-  ret <32 x i32> %v4
+  %v0 = load <32 x i32>, <32 x i32>* %a2, align 128
+  %v1 = tail call <128 x i1> @llvm.hexagon.V6.vandvrt.128B(<32 x i32> %v0, i32 -1)
+  %v2 = tail call { <32 x i32>, <128 x i1> } @llvm.hexagon.V6.vaddcarry.128B(<32 x i32> %a0, <32 x i32> %a1, <128 x i1> %v1)
+  %v3 = extractvalue { <32 x i32>, <128 x i1> } %v2, 0
+  ret <32 x i32> %v3
 }
 
+define inreg <32 x i32> @f1(<32 x i32> %a0, <32 x i32> %a1, <32 x i32>* %a2) #0 {
 ; CHECK-LABEL: f1:
-; CHECK: v{{[0-9]+}}.w = vsub(v{{[0-9]+}}.w,v{{[0-9]+}}.w,q{{[0-3]}}):carry
-define inreg <32 x i32> @f1(<32 x i32> %a0, <32 x i32> %a1, i8* nocapture readonly %a2) #0 {
+; CHECK:       // %bb.0: // %b0
+; CHECK-NEXT:    {
+; CHECK-NEXT:     r1 = #-1
+; CHECK-NEXT:     v2 = vmem(r0+#0)
+; CHECK-NEXT:    }
+; CHECK-NEXT:    {
+; CHECK-NEXT:     q0 = vand(v2,r1)
+; CHECK-NEXT:    }
+; CHECK-NEXT:    {
+; CHECK-NEXT:     v0.w = vsub(v0.w,v1.w,q0):carry
+; CHECK-NEXT:     jumpr r31
+; CHECK-NEXT:    }
 b0:
-  %v0 = bitcast i8* %a2 to <32 x i32>*
-  %v1 = load <32 x i32>, <32 x i32>* %v0, align 128
-  %v2 = tail call <128 x i1> @llvm.hexagon.V6.vandvrt.128B(<32 x i32> %v1, i32 -1)
-  %v3 = tail call { <32 x i32>, <128 x i1> } @llvm.hexagon.V6.vsubcarry.128B(<32 x i32> %a0, <32 x i32> %a1, <128 x i1> %v2)
-  %v4 = extractvalue { <32 x i32>, <128 x i1> } %v3, 0
-  ret <32 x i32> %v4
+  %v0 = load <32 x i32>, <32 x i32>* %a2, align 128
+  %v1 = tail call <128 x i1> @llvm.hexagon.V6.vandvrt.128B(<32 x i32> %v0, i32 -1)
+  %v2 = tail call { <32 x i32>, <128 x i1> } @llvm.hexagon.V6.vsubcarry.128B(<32 x i32> %a0, <32 x i32> %a1, <128 x i1> %v1)
+  %v3 = extractvalue { <32 x i32>, <128 x i1> } %v2, 0
+  ret <32 x i32> %v3
 }
 
-; Function Attrs: nounwind readnone
-declare { <32 x i32>, <128 x i1> } @llvm.hexagon.V6.vaddcarry.128B(<32 x i32>, <32 x i32>, <128 x i1>) #1
+define inreg <32 x i32> @f2(<32 x i32> %a0, <32 x i32> %a1) #0 {
+; CHECK-LABEL: f2:
+; CHECK:       // %bb.0: // %b0
+; CHECK-NEXT:    {
+; CHECK-NEXT:     v0.w,q0 = vadd(v0.w,v1.w):carry
+; CHECK-NEXT:     jumpr r31
+; CHECK-NEXT:    }
+b0:
+  %v0 = tail call { <32 x i32>, <128 x i1> } @llvm.hexagon.V6.vaddcarryo.128B(<32 x i32> %a0, <32 x i32> %a1)
+  %v1 = extractvalue { <32 x i32>, <128 x i1> } %v0, 0
+  ret <32 x i32> %v1
+}
 
-; Function Attrs: nounwind readnone
+define inreg <32 x i32> @f3(<32 x i32> %a0, <32 x i32> %a1) #0 {
+; CHECK-LABEL: f3:
+; CHECK:       // %bb.0: // %b0
+; CHECK-NEXT:    {
+; CHECK-NEXT:     v0.w,q0 = vsub(v0.w,v1.w):carry
+; CHECK-NEXT:     jumpr r31
+; CHECK-NEXT:    }
+b0:
+  %v0 = tail call { <32 x i32>, <128 x i1> } @llvm.hexagon.V6.vsubcarryo.128B(<32 x i32> %a0, <32 x i32> %a1)
+  %v1 = extractvalue { <32 x i32>, <128 x i1> } %v0, 0
+  ret <32 x i32> %v1
+}
+
+declare { <32 x i32>, <128 x i1> } @llvm.hexagon.V6.vaddcarry.128B(<32 x i32>, <32 x i32>, <128 x i1>) #1
 declare { <32 x i32>, <128 x i1> } @llvm.hexagon.V6.vsubcarry.128B(<32 x i32>, <32 x i32>, <128 x i1>) #1
+declare { <32 x i32>, <128 x i1> } @llvm.hexagon.V6.vaddcarryo.128B(<32 x i32>, <32 x i32>) #1
+declare { <32 x i32>, <128 x i1> } @llvm.hexagon.V6.vsubcarryo.128B(<32 x i32>, <32 x i32>) #1
 
-; Function Attrs: nounwind readnone
 declare <128 x i1> @llvm.hexagon.V6.vandvrt.128B(<32 x i32>, i32) #1
 
-attributes #0 = { nounwind "target-cpu"="hexagonv65" "target-features"="+hvxv65,+hvx-length128b" }
+attributes #0 = { nounwind "target-cpu"="hexagonv66" "target-features"="+hvxv66,+hvx-length128b" }
 attributes #1 = { nounwind readnone }

diff --git a/llvm/test/CodeGen/Hexagon/hvx-dual-output.ll b/llvm/test/CodeGen/Hexagon/hvx-dual-output.ll
index cb859aa..8c1e193 100644 (file)
--- a/llvm/test/CodeGen/Hexagon/hvx-dual-output.ll
+++ b/llvm/test/CodeGen/Hexagon/hvx-dual-output.ll
@@ -1,39 +1,84 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -march=hexagon < %s | FileCheck %s
 
 ; Test that we compile the HVX dual output intrinsics.
 
+define inreg <16 x i32> @f0(<16 x i32> %a0, <16 x i32> %a1, <16 x i32>* %a2) #0 {
 ; CHECK-LABEL: f0:
-; CHECK: v{{[0-9]+}}.w = vadd(v{{[0-9]+}}.w,v{{[0-9]+}}.w,q{{[0-3]}}):carry
-define inreg <16 x i32> @f0(<16 x i32> %a0, <16 x i32> %a1, i8* nocapture readonly %a2) #0 {
+; CHECK:       // %bb.0: // %b0
+; CHECK-NEXT:    {
+; CHECK-NEXT:     r1 = #-1
+; CHECK-NEXT:     v2 = vmem(r0+#0)
+; CHECK-NEXT:    }
+; CHECK-NEXT:    {
+; CHECK-NEXT:     q0 = vand(v2,r1)
+; CHECK-NEXT:    }
+; CHECK-NEXT:    {
+; CHECK-NEXT:     v0.w = vadd(v0.w,v1.w,q0):carry
+; CHECK-NEXT:     jumpr r31
+; CHECK-NEXT:    }
 b0:
-  %v0 = bitcast i8* %a2 to <16 x i32>*
-  %v1 = load <16 x i32>, <16 x i32>* %v0, align 64
-  %v2 = tail call <64 x i1> @llvm.hexagon.V6.vandvrt(<16 x i32> %v1, i32 -1)
-  %v3 = tail call { <16 x i32>, <64 x i1> } @llvm.hexagon.V6.vaddcarry(<16 x i32> %a0, <16 x i32> %a1, <64 x i1> %v2)
-  %v4 = extractvalue { <16 x i32>, <64 x i1> } %v3, 0
-  ret <16 x i32> %v4
+  %v0 = load <16 x i32>, <16 x i32>* %a2, align 64
+  %v1 = tail call <64 x i1> @llvm.hexagon.V6.vandvrt(<16 x i32> %v0, i32 -1)
+  %v2 = tail call { <16 x i32>, <64 x i1> } @llvm.hexagon.V6.vaddcarry(<16 x i32> %a0, <16 x i32> %a1, <64 x i1> %v1)
+  %v3 = extractvalue { <16 x i32>, <64 x i1> } %v2, 0
+  ret <16 x i32> %v3
 }
 
+define inreg <16 x i32> @f1(<16 x i32> %a0, <16 x i32> %a1, <16 x i32>* %a2) #0 {
 ; CHECK-LABEL: f1:
-; CHECK: v{{[0-9]+}}.w = vsub(v{{[0-9]+}}.w,v{{[0-9]+}}.w,q{{[0-3]}}):carry
-define inreg <16 x i32> @f1(<16 x i32> %a0, <16 x i32> %a1, i8* nocapture readonly %a2) #0 {
+; CHECK:       // %bb.0: // %b0
+; CHECK-NEXT:    {
+; CHECK-NEXT:     r1 = #-1
+; CHECK-NEXT:     v2 = vmem(r0+#0)
+; CHECK-NEXT:    }
+; CHECK-NEXT:    {
+; CHECK-NEXT:     q0 = vand(v2,r1)
+; CHECK-NEXT:    }
+; CHECK-NEXT:    {
+; CHECK-NEXT:     v0.w = vsub(v0.w,v1.w,q0):carry
+; CHECK-NEXT:     jumpr r31
+; CHECK-NEXT:    }
 b0:
-  %v0 = bitcast i8* %a2 to <16 x i32>*
-  %v1 = load <16 x i32>, <16 x i32>* %v0, align 64
-  %v2 = tail call <64 x i1> @llvm.hexagon.V6.vandvrt(<16 x i32> %v1, i32 -1)
-  %v3 = tail call { <16 x i32>, <64 x i1> } @llvm.hexagon.V6.vsubcarry(<16 x i32> %a0, <16 x i32> %a1, <64 x i1> %v2)
-  %v4 = extractvalue { <16 x i32>, <64 x i1> } %v3, 0
-  ret <16 x i32> %v4
+  %v0 = load <16 x i32>, <16 x i32>* %a2, align 64
+  %v1 = tail call <64 x i1> @llvm.hexagon.V6.vandvrt(<16 x i32> %v0, i32 -1)
+  %v2 = tail call { <16 x i32>, <64 x i1> } @llvm.hexagon.V6.vsubcarry(<16 x i32> %a0, <16 x i32> %a1, <64 x i1> %v1)
+  %v3 = extractvalue { <16 x i32>, <64 x i1> } %v2, 0
+  ret <16 x i32> %v3
 }
 
-; Function Attrs: nounwind readnone
-declare { <16 x i32>, <64 x i1> } @llvm.hexagon.V6.vaddcarry(<16 x i32>, <16 x i32>, <64 x i1>) #1
+define inreg <16 x i32> @f2(<16 x i32> %a0, <16 x i32> %a1) #0 {
+; CHECK-LABEL: f2:
+; CHECK:       // %bb.0: // %b0
+; CHECK-NEXT:    {
+; CHECK-NEXT:     v0.w,q0 = vadd(v0.w,v1.w):carry
+; CHECK-NEXT:     jumpr r31
+; CHECK-NEXT:    }
+b0:
+  %v0 = tail call { <16 x i32>, <64 x i1> } @llvm.hexagon.V6.vaddcarryo(<16 x i32> %a0, <16 x i32> %a1)
+  %v1 = extractvalue { <16 x i32>, <64 x i1> } %v0, 0
+  ret <16 x i32> %v1
+}
 
-; Function Attrs: nounwind readnone
+define inreg <16 x i32> @f3(<16 x i32> %a0, <16 x i32> %a1) #0 {
+; CHECK-LABEL: f3:
+; CHECK:       // %bb.0: // %b0
+; CHECK-NEXT:    {
+; CHECK-NEXT:     v0.w,q0 = vsub(v0.w,v1.w):carry
+; CHECK-NEXT:     jumpr r31
+; CHECK-NEXT:    }
+b0:
+  %v0 = tail call { <16 x i32>, <64 x i1> } @llvm.hexagon.V6.vsubcarryo(<16 x i32> %a0, <16 x i32> %a1)
+  %v1 = extractvalue { <16 x i32>, <64 x i1> } %v0, 0
+  ret <16 x i32> %v1
+}
+
+declare { <16 x i32>, <64 x i1> } @llvm.hexagon.V6.vaddcarry(<16 x i32>, <16 x i32>, <64 x i1>) #1
 declare { <16 x i32>, <64 x i1> } @llvm.hexagon.V6.vsubcarry(<16 x i32>, <16 x i32>, <64 x i1>) #1
+declare { <16 x i32>, <64 x i1> } @llvm.hexagon.V6.vaddcarryo(<16 x i32>, <16 x i32>) #1
+declare { <16 x i32>, <64 x i1> } @llvm.hexagon.V6.vsubcarryo(<16 x i32>, <16 x i32>) #1
 
-; Function Attrs: nounwind readnone
 declare <64 x i1> @llvm.hexagon.V6.vandvrt(<16 x i32>, i32) #1
 
-attributes #0 = { nounwind "target-cpu"="hexagonv65" "target-features"="+hvxv65,+hvx-length64b" }
+attributes #0 = { nounwind "target-cpu"="hexagonv66" "target-features"="+hvxv66,+hvx-length64b" }
 attributes #1 = { nounwind readnone }