arch64: Add optional operand register pair support tests

Add tests to cover the full range of behaviors observed around
optional register operands for the `tlbip' and `sysp' instructions,
namely:

  * Not all `tlbip' operations take GPR operands.  When this is the
  case, we should check that neither optional operand was supplied.
  * When a `tlbip' operation is labeled with the `F_HASXT' flag, xzr
  is not a valid optional operand.  In such case, at least the fist
  optional register needs to be specified with a non-xzr value.
  * The first operand for both insns should be either xzr or an
  even-numbered register (n % 2 == 0).  In the former scenario, the
  second operand should default to xzr too, while in the latter, it
  should default to n + 1.

diff --git a/gas/testsuite/gas/aarch64/illegal-sysp-tlbip-optional.d b/gas/testsuite/gas/aarch64/illegal-sysp-tlbip-optional.d
new file mode 100644 (file)
index 0000000..0bf5af4
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/illegal-sysp-tlbip-optional.d
@@ -0,0 +1,4 @@
+#name: Illegal optional operand pair use
+#as: -mno-verbose-error
+#source: illegal-sysp-tlbip-optional.s
+#error_output: illegal-sysp-tlbip-optional.l

diff --git a/gas/testsuite/gas/aarch64/illegal-sysp-tlbip-optional.l b/gas/testsuite/gas/aarch64/illegal-sysp-tlbip-optional.l
new file mode 100644 (file)
index 0000000..6945074
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/illegal-sysp-tlbip-optional.l
@@ -0,0 +1,4 @@
+[^:]*: Assembler messages:
+[^:]*:5: Error: missing register at operand 2 -- `tlbip vale3nxs'
+[^:]*:9: Error: extraneous register at operand 2 -- `tlbip paall,x0'
+[^:]*:10: Error: extraneous register at operand 2 -- `tlbip paall,x0,x1'

diff --git a/gas/testsuite/gas/aarch64/illegal-sysp-tlbip-optional.s b/gas/testsuite/gas/aarch64/illegal-sysp-tlbip-optional.s
new file mode 100644 (file)
index 0000000..1e02b71
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/illegal-sysp-tlbip-optional.s
@@ -0,0 +1,10 @@
+       .arch armv9.4-a+d128
+
+       /* TLBIP operands marked with the F_HASXT don not allow xzr to be used
+       as GPR arguments and so require at least one register to be specified.  */
+       tlbip   vale3nxs
+
+       /* Conversely, those without the flag do not allow us to specify registers,
+       so the only accepted alternative is the complete omission of optional ops.  */
+       tlbip   paall, x0
+       tlbip   paall, x0, x1

diff --git a/gas/testsuite/gas/aarch64/sysp-tlbip-optional.d b/gas/testsuite/gas/aarch64/sysp-tlbip-optional.d
new file mode 100644 (file)
index 0000000..977dedb
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sysp-tlbip-optional.d
@@ -0,0 +1,17 @@
+#objdump: -dr
+
+.*
+
+Disassembly of section \.text:
+
+0+ <\.text>:
+[^:]*: d54e97a0        sysp    #6, C9, C7, #5, x0, x1
+[^:]*: d54e97a0        sysp    #6, C9, C7, #5, x0, x1
+[^:]*: d54e97a2        sysp    #6, C9, C7, #5, x2, x3
+[^:]*: d54e97a2        sysp    #6, C9, C7, #5, x2, x3
+[^:]*: d54e879f        sysp    #6, C8, C7, #4
+[^:]*: d54e97bf        sysp    #6, C9, C7, #5
+[^:]*: d54e97a0        sysp    #6, C9, C7, #5, x0, x1
+[^:]*: d54e97a0        sysp    #6, C9, C7, #5, x0, x1
+[^:]*: d54e97a2        sysp    #6, C9, C7, #5, x2, x3
+[^:]*: d54e97a2        sysp    #6, C9, C7, #5, x2, x3

diff --git a/gas/testsuite/gas/aarch64/sysp-tlbip-optional.s b/gas/testsuite/gas/aarch64/sysp-tlbip-optional.s
new file mode 100644 (file)
index 0000000..3635db1
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sysp-tlbip-optional.s
@@ -0,0 +1,22 @@
+       .arch armv9.4-a+d128
+
+       /* TLBIP operands marked with the F_HASXT don not allow xzr to be used
+       as GPR arguments and so require at least one register to be specified.  */
+       tlbip   vale3nxs, x0
+       tlbip   vale3nxs, x0, x1
+       tlbip   vale3nxs, x2
+       tlbip   vale3nxs, x2, x3
+
+
+       /* Conversely, those without the flag do not allow us to specify registers,
+       so the only accepted alternative is the complete omission of optional ops.  */
+       tlbip   paall
+
+       /* No such checking is carried out when the same instruction is issued
+       directly via the sysp implementation defined maintenance instruction,
+       such that both GRPs are optional.  */
+       sysp    #6, C9, C7, #5
+       sysp    #6, C9, C7, #5, x0
+       sysp    #6, C9, C7, #5, x0, x1
+       sysp    #6, c9, c7, #5, x2
+       sysp    #6, c9, c7, #5, x2, x3