Merge branch 'master' of git://git.denx.de/u-boot-arm

diff --combined arch/arm/Kconfig
index aaf800f,f933123..106aed9
--- 1/arch/arm/Kconfig
--- 2/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@@ -2,11 -2,9 +2,11 @@@ menu "ARM architecture
        depends on ARM
  
  config SYS_ARCH
 -      string
        default "arm"
  
 +config ARM64
 +      bool
 +
  choice
        prompt "Target select"
  
@@@ -426,6 -424,9 +426,9 @@@ config OMAP54X
  config RMOBILE
        bool "Renesas ARM SoCs"
  
+ config TARGET_CM_FX6
+       bool "Support cm_fx6"
+ 
  config TARGET_S5P_GONI
        bool "Support s5p_goni"
  
@@@ -462,21 -463,15 +465,21 @@@ config TEGR
  
  config TARGET_VEXPRESS_AEMV8A
        bool "Support vexpress_aemv8a"
 -
 -config TARGET_VEXPRESS_AEMV8A_SEMI
 -      bool "Support vexpress_aemv8a_semi"
 +      select ARM64
  
  config TARGET_LS2085A_EMU
        bool "Support ls2085a_emu"
 +      select ARM64
  
  config TARGET_LS2085A_SIMU
        bool "Support ls2085a_simu"
 +      select ARM64
 +
 +config TARGET_LS1021AQDS
 +      bool "Support ls1021aqds_nor"
 +
 +config TARGET_LS1021ATWR
 +      bool "Support ls1021atwr_nor"
  
  config TARGET_BALLOON3
        bool "Support balloon3"
@@@ -519,8 -514,6 +522,8 @@@ config TARGET_JORNAD
  
  endchoice
  
 +source "arch/arm/cpu/armv8/Kconfig"
 +
  source "arch/arm/cpu/arm926ejs/davinci/Kconfig"
  
  source "arch/arm/cpu/armv7/exynos/Kconfig"
@@@ -589,6 -582,7 +592,7 @@@ source "board/cirrus/edb93xx/Kconfig
  source "board/cm4008/Kconfig"
  source "board/cm41xx/Kconfig"
  source "board/compulab/cm_t335/Kconfig"
+ source "board/compulab/cm_fx6/Kconfig"
  source "board/congatec/cgtqmx6eval/Kconfig"
  source "board/creative/xfi3/Kconfig"
  source "board/davedenx/qong/Kconfig"
@@@ -604,8 -598,6 +608,8 @@@ source "board/eukrea/cpu9260/Kconfig
  source "board/eukrea/cpuat91/Kconfig"
  source "board/faraday/a320evb/Kconfig"
  source "board/freescale/ls2085a/Kconfig"
 +source "board/freescale/ls1021aqds/Kconfig"
 +source "board/freescale/ls1021atwr/Kconfig"
  source "board/freescale/mx23evk/Kconfig"
  source "board/freescale/mx25pdk/Kconfig"
  source "board/freescale/mx28evk/Kconfig"

diff --combined drivers/serial/serial_lpuart.c
index b0c6f6f,0a5e159..63fc388
--- 1/drivers/serial/serial_lpuart.c
--- 2/drivers/serial/serial_lpuart.c
+++ b/drivers/serial/serial_lpuart.c
@@@ -14,37 -14,18 +14,42 @@@
  
  #define US1_TDRE        (1 << 7)
  #define US1_RDRF        (1 << 5)
+ #define US1_OR          (1 << 3)
  #define UC2_TE          (1 << 3)
  #define UC2_RE          (1 << 2)
+ #define CFIFO_TXFLUSH   (1 << 7)
+ #define CFIFO_RXFLUSH   (1 << 6)
+ #define SFIFO_RXOF      (1 << 2)
+ #define SFIFO_RXUF      (1 << 0)
  
 +#define STAT_LBKDIF   (1 << 31)
 +#define STAT_RXEDGIF  (1 << 30)
 +#define STAT_TDRE     (1 << 23)
 +#define STAT_RDRF     (1 << 21)
 +#define STAT_IDLE     (1 << 20)
 +#define STAT_OR               (1 << 19)
 +#define STAT_NF               (1 << 18)
 +#define STAT_FE               (1 << 17)
 +#define STAT_PF               (1 << 16)
 +#define STAT_MA1F     (1 << 15)
 +#define STAT_MA2F     (1 << 14)
 +#define STAT_FLAGS    (STAT_LBKDIF | STAT_RXEDGIF | STAT_IDLE | STAT_OR | \
 +                      STAT_NF | STAT_FE | STAT_PF | STAT_MA1F | STAT_MA2F)
 +
 +#define CTRL_TE               (1 << 19)
 +#define CTRL_RE               (1 << 18)
 +
 +#define FIFO_TXFE             0x80
 +#define FIFO_RXFE             0x40
 +
 +#define WATER_TXWATER_OFF     1
 +#define WATER_RXWATER_OFF     16
 +
  DECLARE_GLOBAL_DATA_PTR;
  
  struct lpuart_fsl *base = (struct lpuart_fsl *)LPUART_BASE;
  
 +#ifndef CONFIG_LPUART_32B_REG
  static void lpuart_serial_setbrg(void)
  {
        u32 clk = mxc_get_clock(MXC_UART_CLK);
@@@ -62,14 -43,10 +67,10 @@@
  
  static int lpuart_serial_getc(void)
  {
-       u8 status;
- 
-       while (!(__raw_readb(&base->us1) & US1_RDRF))
+       while (!(__raw_readb(&base->us1) & (US1_RDRF | US1_OR)))
                WATCHDOG_RESET();
  
-       status = __raw_readb(&base->us1);
-       status |= US1_RDRF;
-       __raw_writeb(status, &base->us1);
+       barrier();
  
        return __raw_readb(&base->ud);
  }
@@@ -112,6 -89,12 +113,12 @@@ static int lpuart_serial_init(void
        __raw_writeb(0, &base->umodem);
        __raw_writeb(0, &base->uc1);
  
+       /* Disable FIFO and flush buffer */
+       __raw_writeb(0x0, &base->upfifo);
+       __raw_writeb(0x0, &base->utwfifo);
+       __raw_writeb(0x1, &base->urwfifo);
+       __raw_writeb(CFIFO_TXFLUSH | CFIFO_RXFLUSH, &base->ucfifo);
+ 
        /* provide data bits, parity, stop bit, etc */
  
        serial_setbrg();
@@@ -131,107 -114,13 +138,107 @@@ static struct serial_device lpuart_seri
        .getc = lpuart_serial_getc,
        .tstc = lpuart_serial_tstc,
  };
 +#else
 +static void lpuart32_serial_setbrg(void)
 +{
 +      u32 clk = CONFIG_SYS_CLK_FREQ;
 +      u32 sbr;
 +
 +      if (!gd->baudrate)
 +              gd->baudrate = CONFIG_BAUDRATE;
 +
 +      sbr = (clk / (16 * gd->baudrate));
 +      /* place adjustment later - n/32 BRFA */
 +
 +      out_be32(&base->baud, sbr);
 +}
 +
 +static int lpuart32_serial_getc(void)
 +{
 +      u32 stat;
 +
 +      while (((stat = in_be32(&base->stat)) & STAT_RDRF) == 0) {
 +              out_be32(&base->stat, STAT_FLAGS);
 +              WATCHDOG_RESET();
 +      }
 +
 +      return in_be32(&base->data) & 0x3ff;
 +}
 +
 +static void lpuart32_serial_putc(const char c)
 +{
 +      if (c == '\n')
 +              serial_putc('\r');
 +
 +      while (!(in_be32(&base->stat) & STAT_TDRE))
 +              WATCHDOG_RESET();
 +
 +      out_be32(&base->data, c);
 +}
 +
 +/*
 + * Test whether a character is in the RX buffer
 + */
 +static int lpuart32_serial_tstc(void)
 +{
 +      if ((in_be32(&base->water) >> 24) == 0)
 +              return 0;
 +
 +      return 1;
 +}
 +
 +/*
 + * Initialise the serial port with the given baudrate. The settings
 + * are always 8 data bits, no parity, 1 stop bit, no start bits.
 + */
 +static int lpuart32_serial_init(void)
 +{
 +      u8 ctrl;
 +
 +      ctrl = in_be32(&base->ctrl);
 +      ctrl &= ~CTRL_RE;
 +      ctrl &= ~CTRL_TE;
 +      out_be32(&base->ctrl, ctrl);
 +
 +      out_be32(&base->modir, 0);
 +      out_be32(&base->fifo, ~(FIFO_TXFE | FIFO_RXFE));
 +
 +      out_be32(&base->match, 0);
 +      /* provide data bits, parity, stop bit, etc */
 +
 +      serial_setbrg();
 +
 +      out_be32(&base->ctrl, CTRL_RE | CTRL_TE);
 +
 +      return 0;
 +}
 +
 +static struct serial_device lpuart32_serial_drv = {
 +      .name = "lpuart32_serial",
 +      .start = lpuart32_serial_init,
 +      .stop = NULL,
 +      .setbrg = lpuart32_serial_setbrg,
 +      .putc = lpuart32_serial_putc,
 +      .puts = default_serial_puts,
 +      .getc = lpuart32_serial_getc,
 +      .tstc = lpuart32_serial_tstc,
 +};
 +#endif
  
  void lpuart_serial_initialize(void)
  {
 +#ifdef CONFIG_LPUART_32B_REG
 +      serial_register(&lpuart32_serial_drv);
 +#else
        serial_register(&lpuart_serial_drv);
 +#endif
  }
  
  __weak struct serial_device *default_serial_console(void)
  {
 +#ifdef CONFIG_LPUART_32B_REG
 +      return &lpuart32_serial_drv;
 +#else
        return &lpuart_serial_drv;
 +#endif
  }