s5pc11x initial MMC clock = EPLL/2 = 48MHz (MMC0-2)

diff --git a/board/samsung/universal/lowlevel_init.S b/board/samsung/universal/lowlevel_init.S
index 0096a5d..58799bf 100644 (file)
--- a/board/samsung/universal/lowlevel_init.S
+++ b/board/samsung/universal/lowlevel_init.S
@@ -559,6 +559,9 @@ system_clock_init:
        ldr     r1, =0x10001111                 @ A, M, E, VPLL Muxing
        str     r1, [r0, #0x200]                @ S5PC1XX_CLK_SRC0
 
+       ldr     r1, =0x66667777                 @ S5PC110_CLK_SRC4 (UART/MMC)
+       str     r1, [r0, #0x210]
+
        /* OneDRAM(DMC0) clock setting */
        ldr     r1, =0x01000000                 @ ONEDRAM_SEL[25:24] 1 SCLKMPLL
        str     r1, [r0, #0x218]                @ S5PC110_CLK_SRC6

diff --git a/board/samsung/universal/universal.c b/board/samsung/universal/universal.c
index 745ec77..769e3a3 100644 (file)
--- a/board/samsung/universal/universal.c
+++ b/board/samsung/universal/universal.c
@@ -642,10 +642,11 @@ static void check_hw_revision(void)
 
                                        /* Haydn MP0_4[0] == 1 */
                                        gpio_direction_input(&gpio->gpio_mp0_4, 0);
-                                       if (gpio_get_value(&gpio->gpio_mp0_4, 0) == 1) {
+                                       if (gpio_get_value(&gpio->gpio_mp0_4, 0) == 1)
                                                board_rev |= HAYDN_BOARD;
                                        else
                                                board_rev |= SDK_BOARD;
+
                                }
 
                        }
@@ -2714,26 +2715,6 @@ int board_mmc_init(bd_t *bis)
        if (mach_is_wmg160())
                return -1;
 
-       /* MMC0 Clock source = SCLKMPLL */
-       reg = readl(&clk->src4);
-       reg &= ~0xf;
-       reg |= 0x6;
-       writel(reg, &clk->src4);
-
-       reg = readl(&clk->div4);
-       reg &= ~0xf;
-
-       /* set div value near 50MHz */
-       clock = get_pll_clk(MPLL) / 1000000;
-       for (i = 0; i < 0xf; i++) {
-               if ((clock / (i + 1)) <= 50) {
-                       reg |= i << 0;
-                       break;
-               }
-       }
-
-       writel(reg, &clk->div4);
-
        /*
         * MMC0 GPIO
         * GPG0[0]      SD_0_CLK