radeonsi: allow setting any index in radeon_set_sh_reg_idx

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24759>

diff --git a/src/gallium/drivers/radeonsi/si_build_pm4.h b/src/gallium/drivers/radeonsi/si_build_pm4.h
index 425d19c..eba45c4 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_build_pm4.h
+++ b/src/gallium/drivers/radeonsi/si_build_pm4.h
@@ -96,12 +96,12 @@
    radeon_emit(((reg) - SI_SH_REG_OFFSET) >> 2); \
 } while (0)
 
-#define radeon_set_sh_reg_idx3_seq(sctx, reg, num) do { \
+#define radeon_set_sh_reg_idx_seq(sctx, reg, idx, num) do { \
    assert((reg) >= SI_SH_REG_OFFSET && (reg) < SI_SH_REG_END); \
    if ((sctx)->screen->info.uses_kernel_cu_mask) { \
       assert((sctx)->gfx_level >= GFX10); \
       radeon_emit(PKT3(PKT3_SET_SH_REG_INDEX, num, 0)); \
-      radeon_emit((((reg) - SI_SH_REG_OFFSET) >> 2) | (3 << 28)); \
+      radeon_emit((((reg) - SI_SH_REG_OFFSET) >> 2) | ((idx) << 28)); \
    } else { \
       radeon_emit(PKT3(PKT3_SET_SH_REG, num, 0)); \
       radeon_emit(((reg) - SI_SH_REG_OFFSET) >> 2); \
@@ -113,8 +113,8 @@
    radeon_emit(value); \
 } while (0)
 
-#define radeon_set_sh_reg_idx3(sctx, reg, value) do { \
-   radeon_set_sh_reg_idx3_seq(sctx, reg, 1); \
+#define radeon_set_sh_reg_idx(sctx, reg, idx, value) do { \
+   radeon_set_sh_reg_idx_seq(sctx, reg, idx, 1); \
    radeon_emit(value); \
 } while (0)
 
@@ -358,11 +358,11 @@
    } \
 } while (0)
 
-#define radeon_opt_set_sh_reg_idx3(sctx, offset, reg, val) do { \
+#define radeon_opt_set_sh_reg_idx(sctx, offset, reg, idx, val) do { \
    unsigned __value = val; \
    if (((sctx->tracked_regs.other_reg_saved_mask >> (reg)) & 0x1) != 0x1 || \
        sctx->tracked_regs.other_reg_value[reg] != __value) { \
-      radeon_set_sh_reg_idx3(sctx, offset, __value); \
+      radeon_set_sh_reg_idx(sctx, offset, idx, __value); \
       sctx->tracked_regs.other_reg_saved_mask |= BITFIELD_BIT(reg); \
       sctx->tracked_regs.other_reg_value[reg] = __value; \
    } \

diff --git a/src/gallium/drivers/radeonsi/si_state_shaders.cpp b/src/gallium/drivers/radeonsi/si_state_shaders.cpp
index 395c980..7689c7a 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_state_shaders.cpp
+++ b/src/gallium/drivers/radeonsi/si_state_shaders.cpp
@@ -973,14 +973,14 @@ static void si_emit_shader_gs(struct si_context *sctx, unsigned index)
    /* These don't cause any context rolls. */
    radeon_begin_again(&sctx->gfx_cs);
    if (sctx->gfx_level >= GFX7) {
-      radeon_opt_set_sh_reg_idx3(sctx, R_00B21C_SPI_SHADER_PGM_RSRC3_GS,
-                                 SI_TRACKED_SPI_SHADER_PGM_RSRC3_GS,
-                                 shader->gs.spi_shader_pgm_rsrc3_gs);
+      radeon_opt_set_sh_reg_idx(sctx, R_00B21C_SPI_SHADER_PGM_RSRC3_GS,
+                                SI_TRACKED_SPI_SHADER_PGM_RSRC3_GS,
+                                3, shader->gs.spi_shader_pgm_rsrc3_gs);
    }
    if (sctx->gfx_level >= GFX10) {
-      radeon_opt_set_sh_reg_idx3(sctx, R_00B204_SPI_SHADER_PGM_RSRC4_GS,
-                                 SI_TRACKED_SPI_SHADER_PGM_RSRC4_GS,
-                                 shader->gs.spi_shader_pgm_rsrc4_gs);
+      radeon_opt_set_sh_reg_idx(sctx, R_00B204_SPI_SHADER_PGM_RSRC4_GS,
+                                SI_TRACKED_SPI_SHADER_PGM_RSRC4_GS,
+                                3, shader->gs.spi_shader_pgm_rsrc4_gs);
    }
    radeon_end();
 }
@@ -1198,12 +1198,12 @@ static void gfx10_emit_shader_ngg_tail(struct si_context *sctx, struct si_shader
                                  SI_TRACKED_SPI_SHADER_PGM_RSRC4_GS,
                                  shader->gs.spi_shader_pgm_rsrc4_gs);
    } else {
-      radeon_opt_set_sh_reg_idx3(sctx, R_00B21C_SPI_SHADER_PGM_RSRC3_GS,
-                                 SI_TRACKED_SPI_SHADER_PGM_RSRC3_GS,
-                                 shader->ngg.spi_shader_pgm_rsrc3_gs);
-      radeon_opt_set_sh_reg_idx3(sctx, R_00B204_SPI_SHADER_PGM_RSRC4_GS,
-                                 SI_TRACKED_SPI_SHADER_PGM_RSRC4_GS,
-                                 shader->ngg.spi_shader_pgm_rsrc4_gs);
+      radeon_opt_set_sh_reg_idx(sctx, R_00B21C_SPI_SHADER_PGM_RSRC3_GS,
+                                SI_TRACKED_SPI_SHADER_PGM_RSRC3_GS,
+                                3, shader->ngg.spi_shader_pgm_rsrc3_gs);
+      radeon_opt_set_sh_reg_idx(sctx, R_00B204_SPI_SHADER_PGM_RSRC4_GS,
+                                SI_TRACKED_SPI_SHADER_PGM_RSRC4_GS,
+                                3, shader->ngg.spi_shader_pgm_rsrc4_gs);
    }
    radeon_end();
 }